diff options
author | Tom Rini <trini@konsulko.com> | 2024-04-18 10:08:57 -0600 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2024-04-18 10:08:57 -0600 |
commit | cdf0195e90b66f25ed44fa5ed5634ec064e8dcb9 (patch) | |
tree | 0754178ede128c2313a22d5012841e091becdbef /board/cssi/common/common.c | |
parent | cdd20e3f66fe910da0545d3615decf511519b4a6 (diff) | |
parent | 741e30e8c2b837dc92ee2eedec5478afdd83a316 (diff) |
Merge branch 'for-2024.07' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx
This pull request adds support for temperature sensors et FPGA loading
on boards from CS GROUP France.
CI: https://source.denx.de/u-boot/custodians/u-boot-mpc8xx/-/pipelines/20416
Diffstat (limited to 'board/cssi/common/common.c')
-rw-r--r-- | board/cssi/common/common.c | 42 |
1 files changed, 39 insertions, 3 deletions
diff --git a/board/cssi/common/common.c b/board/cssi/common/common.c index 7ecf7726209..0292a9016e8 100644 --- a/board/cssi/common/common.c +++ b/board/cssi/common/common.c @@ -164,7 +164,7 @@ int checkboard_common(void) void misc_init_r_common(void) { - u8 tmp, far_id; + u8 tmp, far_id, addr; int count = 3; switch (in_8(ADDR_FPGA_R_BASE)) { @@ -173,6 +173,10 @@ void misc_init_r_common(void) if ((in_8(ADDR_FPGA_R_BASE + 0x31) & FPGA_R_ACQ_AL_FAV) == 0) env_set("bootdelay", "60"); + addr = in_8(ADDR_FPGA_R_BASE + 0x43); + printf("Board address: 0x%2.2x (System %d Rack %d Slot %d)\n", + addr, addr >> 7, (addr >> 4) & 7, addr & 15); + env_set("config", CFG_BOARD_MCR3000_2G); env_set("hostname", CFG_BOARD_MCR3000_2G); break; @@ -208,12 +212,44 @@ void misc_init_r_common(void) } } +static void iop_setup_fpgam_common(void) +{ + u8 far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5; + + if (far_id == FAR_CASRSA) { + /* + * PFDIR[15] = 0 [0x01] + * PFDIR[14] = 1 [0x02] + * PFDIR[13] = 1 [0x04] + */ + clrsetbits_8(ADDR_FPGA_R_BASE + 0x37, 0x01, 0x06); + /* + * PFODR[15] = 1 [0x01] + * PFODR[14] = 0 [0x02] + * PFODR[13] = 0 [0x04] + */ + clrsetbits_8(ADDR_FPGA_R_BASE + 0x39, 0x06, 0x01); + /* + * PFDAT[15] = 0 [0x01] + * PFDAT[14] = 1 [0x02] + * PFDAT[13] = 1 [0x04] + * PFDAT[12] = 1 [0x08] + */ + clrsetbits_8(ADDR_FPGA_R_BASE + 0x3B, 0x01, 0x0E); + + /* Setup TOR_OUT */ + out_8(ADDR_FPGA_R_BASE + 0x32, 0x2A); + } +} + void iop_setup_common(void) { u8 type = in_8(ADDR_FPGA_R_BASE); - if (type == TYPE_MCR) + if (type == TYPE_MCR) { iop_setup_mcr(); - else if (type == TYPE_MIAE) + } else if (type == TYPE_MIAE) { iop_setup_miae(); + iop_setup_fpgam_common(); + } } |