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authorTom Rini <trini@konsulko.com>2023-12-15 08:22:20 -0500
committerTom Rini <trini@konsulko.com>2023-12-15 08:22:31 -0500
commit3ac22891cfc0dc6d8eec25d2b0fbdd2eb8f3d3ed (patch)
treed83a8295f07199ddf80c0b10f9c7c604b5e02a03 /board/data_modul/common/common.c
parent27089f1e4d11fd7e0619097b59258d0428cde2ac (diff)
parent4f7122ca1580602399afc30f94f4b37f79e4d662 (diff)
Merge tag 'u-boot-imx-20231214' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Fix for i.MX8M Plus eDM SBC DDR timings with inline ECC - Switch to FPWM mode on Data Modul i.MX8M Plus eDM SBC so that DRAM EDAC detects more correctable errors - Fix for imx8mp-venice board DDR initialization
Diffstat (limited to 'board/data_modul/common/common.c')
-rw-r--r--board/data_modul/common/common.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c
index bf9a11472d1..a6761c21d40 100644
--- a/board/data_modul/common/common.c
+++ b/board/data_modul/common/common.c
@@ -30,6 +30,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7
+
u8 dmo_get_memcfg(void)
{
struct gpio_desc gpio[4];
@@ -58,8 +60,16 @@ u8 dmo_get_memcfg(void)
int board_phys_sdram_size(phys_size_t *size)
{
u8 memcfg = dmo_get_memcfg();
+ u8 ecc = 0;
+
+ *size = 4ULL >> ((memcfg >> 1) & 0x3);
+
+ if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) {
+ /* 896 MiB, i.e. 1 GiB without 12.5% reserved for in-band ECC */
+ ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK;
+ }
- *size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G;
+ *size *= SZ_1G - (ecc ? (SZ_1G / 8) : 0);
return 0;
}
@@ -100,6 +110,12 @@ static void spl_dram_init(struct dram_timing_info *dram_timing_info[8])
}
ddr_init(dram_timing_info[memcfg]);
+
+ if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) {
+ printf("DDR: Inline ECC %sabled\n",
+ (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
+ "en" : "dis");
+ }
}
void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad,