diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2023-01-31 16:42:30 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2023-03-29 20:15:42 +0200 |
| commit | fd3cb1d977292be9f0ca803f869108c222bbea36 (patch) | |
| tree | b5e35ae2171efb654e12445427f3aa3381c89fc8 /board/freescale/imx8ulp_evk/ddr_init.c | |
| parent | a29383da7231774808c6034ca68b0231520058a4 (diff) | |
imx8ulp_evk: Update the DDR timing
Update the dram timing to support PLL bypass mode
for F1.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'board/freescale/imx8ulp_evk/ddr_init.c')
0 files changed, 0 insertions, 0 deletions