diff options
| author | Tom Rini <trini@ti.com> | 2015-01-22 20:04:17 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-01-22 20:04:17 -0500 |
| commit | ec0cc98f2cb7fa217ed0a1a54978e2d8f2fbc20c (patch) | |
| tree | 6bfa9a96dcad59fc12f8825cfaf99c09680075f5 /board/freescale/t102xrdb/ddr.c | |
| parent | 032c6867a2925c95897afe07d1f0678114254cf6 (diff) | |
| parent | db4a1767c09a4696792204d1cac33631cb38424e (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board/freescale/t102xrdb/ddr.c')
| -rw-r--r-- | board/freescale/t102xrdb/ddr.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index a20330b1d01..a2a8f4ccf04 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -11,6 +11,7 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/fsl_law.h> +#include <asm/mpc85xx_gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -136,6 +137,19 @@ found: #endif } +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(cpld_base + 0x17, 0x40); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -150,5 +164,10 @@ phys_size_t initdram(int board_type) /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + return dram_size; } |