venice: lpddr4_timing_imx8mm: add 4gb single die support

Add dram support for the MT53E1G32D2FW-046 RevC part which is a single die
32Gbit density part vs RevA/B which were dual-die parts:
 - use a previously unused EEPROM byte to denote a variant of the
   base config to be patched
 - add a dram description string
 - return the board struct from eeprom_init and pass it to the
   spl_dram_init function so that it has access to the EEPROM
 - move ddr_init into the spl_dram_init so that it can be patched
   in the per-soc init function

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

1 files changed, 12 insertions, 1 deletions

diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c
index 36c4cb147e8..f2d5d9ce565 100644
--- a/board/gateworks/venice/lpddr4_timing_imx8mp.c
+++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c
@@ -1,8 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0+
 
 #include <linux/kernel.h>
+#include <string.h>
 #include <asm/arch/ddr.h>
 
+#include "eeprom.h"
+
 /*
  * Generated code from MX8M_DDR_tool v3.30 using MX8M_Plus RPAv7
  */
@@ -2378,21 +2381,29 @@ static struct dram_timing_info dram_timing_4gb_dual_die = {
 	.fsp_table = { 4000, 400, 100, },
 };
 
-struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
+struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info,
+				       char *dram_desc, size_t sz_desc)
 {
 	struct dram_timing_info *dram_timing;
+	int sizemb = (16 << info->sdram_size);
 
 	switch (sizemb) {
 	case 1024:
 		dram_timing = &dram_timing_1gb_single_die;
+		if (dram_desc)
+			strlcpy(dram_desc, "single-die", sz_desc);
 		break;
 	case 4096:
 		dram_timing = &dram_timing_4gb_dual_die;
+		if (dram_desc)
+			strlcpy(dram_desc, "dual-die", sz_desc);
 		break;
 	default:
 		printf("unsupported");
 		dram_timing = &dram_timing_4gb_dual_die;
 	}
+	if (ddr_init(dram_timing))
+		return NULL;
 
 	return dram_timing;
 }