diff options
author | Tom Rini <trini@konsulko.com> | 2022-06-20 08:08:29 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2022-06-20 08:08:29 -0400 |
commit | a9e90d357bbf539e07c1d971161e027eb335183e (patch) | |
tree | c0994366667aa4acdd55b8e5054d83a0560eb8a2 /board/kontron/sl28/ddr.c | |
parent | 98c4828740f4944462b7d9608b95d5b73850c7b0 (diff) | |
parent | 7bc683afda5ede82cfcace77cecab1891d6d93ff (diff) |
Merge tag 'fsl-qoriq-2022-6-20-v2' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
Layerscape:
add sfp driver
Kconfig cleanup
sl28 board update
support hdp firmware loading
powerpc:
dts update for p2020
p1_p2_rdb_pc board update
fsl_esdhc fallback to 1-bit mode support
Diffstat (limited to 'board/kontron/sl28/ddr.c')
-rw-r--r-- | board/kontron/sl28/ddr.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index 41426996ab9..315d9f99c71 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -54,6 +54,9 @@ static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = { .ddr_cdr1 = 0x80040000, .ddr_cdr2 = 0x0000bc01, + + /* Erratum A-009942, set optimal CPO value */ + .debug[28] = 0x00700040, }; int fsl_initdram(void) @@ -66,11 +69,17 @@ int fsl_initdram(void) dram_size = 0x80000000; ddr_cfg_regs.cs[1].bnds = 0; ddr_cfg_regs.cs[1].config = 0; - ddr_cfg_regs.cs[1].config_2 = 0; break; case GPPORCR1_MEM_4GB_CS0_1: dram_size = 0x100000000ULL; break; + case GPPORCR1_MEM_8GB_CS0_1: + dram_size = 0x200000000ULL; + ddr_cfg_regs.cs[0].bnds = 0x000000ff; + ddr_cfg_regs.cs[0].config = 0x80044403; + ddr_cfg_regs.cs[1].bnds = 0x010001ff; + ddr_cfg_regs.cs[1].config = 0x80044403; + break; case GPPORCR1_MEM_512MB_CS0: dram_size = 0x20000000; fallthrough; /* for now */ @@ -80,7 +89,6 @@ int fsl_initdram(void) case GPPORCR1_MEM_4GB_CS0_2: dram_size = 0x100000000ULL; fallthrough; /* for now */ - case GPPORCR1_MEM_8GB_CS0_1: case GPPORCR1_MEM_8GB_CS0_1_2_3: dram_size = 0x200000000ULL; fallthrough; /* for now */ |