diff options
| author | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2023-05-31 20:10:28 +0200 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2023-06-08 22:26:51 +0200 |
| commit | a4fc6ee9e70eae21d4470b52d866442a4a068c79 (patch) | |
| tree | 787ba8536fbe13bdb3b227a41c10e9ed7db450f3 /board/renesas/rcar-common/common.c | |
| parent | 3aa4fb12f4abd31bce7fe6294dd47fd0966a791a (diff) | |
ARM: rmobile: Deduplicate R-Car Gen3/Gen4 reset_cpu()
The reset_cpu() implementation is basically the same across Gen3
SoCs and identical across Gen4 SoCs. Introduce weak default for
reset_cpu(), so that it does not have to be duplicated in every
board file again.
There is a slight difference for CA53 only systems, like E3 and D3,
which now check MIDR for CPU ID first just like the other systems,
but this is OK since the MIDR always returns CA53 core type and the
correct reset register is written.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Diffstat (limited to 'board/renesas/rcar-common/common.c')
| -rw-r--r-- | board/renesas/rcar-common/common.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index f38453af82c..17940aa9146 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -10,8 +10,10 @@ #include <common.h> #include <dm.h> #include <fdt_support.h> +#include <hang.h> #include <init.h> #include <asm/global_data.h> +#include <asm/io.h> #include <dm/uclass-internal.h> #include <asm/arch/rmobile.h> #include <linux/libfdt.h> @@ -47,6 +49,41 @@ int dram_init_banksize(void) return 0; } +#if defined(CONFIG_RCAR_GEN3) +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_RSTOUTCR (RST_BASE + 0x58) +#define RST_CA57_CODE 0xA5A5000F +#define RST_CA53_CODE 0x5A5A000F + +void __weak reset_cpu(void) +{ + unsigned long midr, cputype; + + asm volatile("mrs %0, midr_el1" : "=r" (midr)); + cputype = (midr >> 4) & 0xfff; + + if (cputype == 0xd03) + writel(RST_CA53_CODE, RST_CA53RESCNT); + else if (cputype == 0xd07) + writel(RST_CA57_CODE, RST_CA57RESCNT); + else + hang(); +} +#elif defined(CONFIG_RCAR_GEN4) +#define RST_BASE 0xE6160000 /* Domain0 */ +#define RST_SRESCR0 (RST_BASE + 0x18) +#define RST_SPRES 0x5AA58000 + +void __weak reset_cpu(void) +{ + writel(RST_SPRES, RST_SRESCR0); +} +#else +#error Neither CONFIG_RCAR_GEN3 nor CONFIG_RCAR_GEN4 are set +#endif + #if defined(CONFIG_OF_BOARD_SETUP) static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node) { |