ARM: rmobile: Update H2 Stout

The H2 Stout port was broken since some time. This patch updates
the H2 Stout port to use modern frameworks, DM, DT probing, SPL
and TPL for the preloading and puts it on par with the M2 Porter
board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

1 files changed, 16 insertions, 119 deletions

diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c
index 3cb16db10f4..d7e81292a0e 100644
--- a/board/renesas/stout/stout.c
+++ b/board/renesas/stout/stout.c
@@ -59,14 +59,7 @@ void s_init(void)
 	qos_init();
 }
 
-#define TMU0_MSTP125	(1 << 25)
-#define SCIFA0_MSTP204	(1 << 4)
-#define SDHI0_MSTP314	(1 << 14)
-#define SDHI2_MSTP312	(1 << 12)
-#define ETHER_MSTP813	(1 << 13)
-
-#define MSTPSR3		0xE6150048
-#define SMSTPCR3	0xE615013C
+#define TMU0_MSTP125	BIT(25)
 
 #define SD2CKCR		0xE6150078
 #define SD2_97500KHZ	0x7
@@ -75,12 +68,6 @@ int board_early_init_f(void)
 {
 	/* TMU0 */
 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-	/* SCIFA0 */
-	mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
-	/* ETHER */
-	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-	/* SDHI0,2 */
-	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312);
 
 	/*
 	 * SD0 clock is set to 97.5MHz by default.
@@ -91,66 +78,37 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#define ETHERNET_PHY_RESET	123	/* GPIO 3 31 */
+
 int board_init(void)
 {
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	/* Init PFC controller */
-	r8a7790_pinmux_init();
-
 	cpld_init();
 
-#ifdef CONFIG_SH_ETHER
-	/* ETHER Enable */
-	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
-	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
-	gpio_request(GPIO_FN_ETH_RXD0, NULL);
-	gpio_request(GPIO_FN_ETH_RXD1, NULL);
-	gpio_request(GPIO_FN_ETH_LINK, NULL);
-	gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
-	gpio_request(GPIO_FN_ETH_MDIO, NULL);
-	gpio_request(GPIO_FN_ETH_TXD1, NULL);
-	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
-	gpio_request(GPIO_FN_ETH_MAGIC, NULL);
-	gpio_request(GPIO_FN_ETH_TXD0, NULL);
-	gpio_request(GPIO_FN_ETH_MDC, NULL);
-	gpio_request(GPIO_FN_IRQ1, NULL);
-
-	gpio_request(GPIO_GP_3_31, NULL); /* PHY_RST */
-	gpio_direction_output(GPIO_GP_3_31, 0);
+	/* Force ethernet PHY out of reset */
+	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+	gpio_direction_output(ETHERNET_PHY_RESET, 0);
 	mdelay(20);
-	gpio_set_value(GPIO_GP_3_31, 1);
-	udelay(1);
-#endif
+	gpio_direction_output(ETHERNET_PHY_RESET, 1);
 
 	return 0;
 }
 
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
 {
-	int ret = -ENODEV;
-
-#ifdef CONFIG_SH_ETHER
-	u32 val;
-	unsigned char enetaddr[6];
-
-	ret = sh_eth_initialize(bis);
-	if (!eth_env_get_enetaddr("ethaddr", enetaddr))
-		return ret;
+	if (fdtdec_setup_memory_size() != 0)
+		return -EINVAL;
 
-	/* Set Mac address */
-	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
-	      enetaddr[2] << 8 | enetaddr[3];
-	writel(val, CXR24);
+	return 0;
+}
 
-	val = enetaddr[4] << 8 | enetaddr[5];
-	writel(val, CXR25);
-#endif
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
 
-	return ret;
+	return 0;
 }
 
 /* Stout has KSZ8041NL/RNL */
@@ -167,67 +125,6 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
-int board_mmc_init(bd_t *bis)
-{
-	int ret = -ENODEV;
-
-#ifdef CONFIG_SH_SDHI
-	gpio_request(GPIO_FN_SD0_DAT0, NULL);
-	gpio_request(GPIO_FN_SD0_DAT1, NULL);
-	gpio_request(GPIO_FN_SD0_DAT2, NULL);
-	gpio_request(GPIO_FN_SD0_DAT3, NULL);
-	gpio_request(GPIO_FN_SD0_CLK, NULL);
-	gpio_request(GPIO_FN_SD0_CMD, NULL);
-	gpio_request(GPIO_FN_SD0_CD, NULL);
-	gpio_request(GPIO_FN_SD2_DAT0, NULL);
-	gpio_request(GPIO_FN_SD2_DAT1, NULL);
-	gpio_request(GPIO_FN_SD2_DAT2, NULL);
-	gpio_request(GPIO_FN_SD2_DAT3, NULL);
-	gpio_request(GPIO_FN_SD2_CLK, NULL);
-	gpio_request(GPIO_FN_SD2_CMD, NULL);
-	gpio_request(GPIO_FN_SD2_CD, NULL);
-
-	/* SDHI0 - needs CPLD mux setup */
-	gpio_request(GPIO_GP_3_30, NULL);
-	gpio_direction_output(GPIO_GP_3_30, 1); /* VLDO3=3.3V */
-	gpio_request(GPIO_GP_5_24, NULL);
-	gpio_direction_output(GPIO_GP_5_24, 1); /* power on */
-
-	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
-			   SH_SDHI_QUIRK_16BIT_BUF);
-	if (ret)
-		return ret;
-
-	/* SDHI2 - needs CPLD mux setup */
-	gpio_request(GPIO_GP_3_29, NULL);
-	gpio_direction_output(GPIO_GP_3_29, 1); /* VLDO4=3.3V */
-	gpio_request(GPIO_GP_5_25, NULL);
-	gpio_direction_output(GPIO_GP_5_25, 1); /* power on */
-
-	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
-#endif
-	return ret;
-}
-
-
-int dram_init(void)
-{
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
-	return 0;
-}
-
 const struct rmobile_sysinfo sysinfo = {
 	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
-
-static const struct sh_serial_platdata serial_platdata = {
-	.base = SCIFA0_BASE,
-	.type = PORT_SCIFA,
-	.clk = CONFIG_MP_CLK_FREQ,
-};
-
-U_BOOT_DEVICE(stout_serials) = {
-	.name = "serial_sh",
-	.platdata = &serial_platdata,
-};