Merge tag 'xilinx-for-v2025.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

AMD/Xilinx changes for v2025.10-rc1

cmd:
- Introduce CMD_HELP Kconfig option

fpga:
- Fix in intel_smd_mb

mini:
- Remove simple-bus driver and description
- Disable CMD_HELP

firmware:
- Fix dependencies
- Switch to new SMC firmware format

cadence qspi:
- Fix read/write STIG mode
- Set tshsl_ns to at least one sclk_ns

sdhci:
- Call sdhci reset if wired

zynqmp-clk:
- Add support for DPLL clock source

zynqmp:
- Sync clock ID bindings with Linux
- defconfig updates
- Enable rng-seed generation

versal:
- Fix clock dependency

versal2:
- defconfig updates
- Enable sysreset

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1 files changed, 32 insertions, 1 deletions

diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 8ffe7429901..ceb58da6d3c 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2014 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -712,3 +712,34 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 }
 
 #endif
+
+#if IS_ENABLED(CONFIG_BOARD_RNG_SEED)
+/* Use hardware rng to seed Linux random. */
+__weak int board_rng_seed(struct abuf *buf)
+{
+	struct udevice *dev;
+	ulong len = 64;
+	u64 *data;
+
+	if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
+		printf("No RNG device\n");
+		return -ENODEV;
+	}
+
+	data = malloc(len);
+	if (!data) {
+		printf("Out of memory\n");
+		return -ENOMEM;
+	}
+
+	if (dm_rng_read(dev, data, len)) {
+		printf("Reading RNG failed\n");
+		free(data);
+		return -EIO;
+	}
+
+	abuf_init_set(buf, data, len);
+
+	return 0;
+}
+#endif