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authorTom Rini <trini@konsulko.com>2025-04-17 07:52:02 -0600
committerTom Rini <trini@konsulko.com>2025-04-17 07:52:02 -0600
commit278be62c052f3a5749c3c7a57bcd307b82dcdc2d (patch)
treedcb621d8d29086f3a0cdef7148f13ce32ebb7fb1 /board/xilinx/versal-net/board.c
parent0f7a4ac96b27fa77b798c6c9598e05cf1654920b (diff)
parent8e25e76fff0698c8268b279af3d7859ed2e14ea5 (diff)
Merge tag 'xilinx-for-v2025.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2025.07-rc1 AMD/Xilinx: - Synchronize enums around tcm_mode - Access bootmode registers via firmware interface - Setup default values for DEBUG_UART - Fix dfu alt buffer clearing - Convert loadpdi command to fpga - Fix board detection code - Minor defconfig updates Versal: - Wire multi_boot register Versal Gen 2: - Enable missing drivers - Wire i2c FRU decoding at start - Wire saving variables to different locations - Disable default DEBUG_UART - Wire USB/UFS boot and fix access via firmware interface - Minor fixes ZynqMP/Kria: - Enable mkfwumdata - Topic board update - Enhance binman configurations - Kria usb update BuR: - Add multiple Zynq based boards cadence_ospi: - Enable device reset fpga: - Add support for loading bitstream for Altera SoCs
Diffstat (limited to 'board/xilinx/versal-net/board.c')
-rw-r--r--board/xilinx/versal-net/board.c19
1 files changed, 18 insertions, 1 deletions
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 4d5913cff1d..65b2a451ad7 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -21,6 +21,8 @@
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
+#include <zynqmp_firmware.h>
+#include <versalpl.h>
#include "../common/board.h"
#include <linux/bitfield.h>
@@ -29,10 +31,21 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_FPGA_VERSALPL)
+static xilinx_desc versalpl = {
+ xilinx_versal_net, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
+ FPGA_LEGACY
+};
+#endif
+
int board_init(void)
{
printf("EL Level:\tEL%d\n", current_el());
+#if defined(CONFIG_FPGA_VERSALPL)
+ fpga_init();
+ fpga_add(fpga_xilinx, &versalpl);
+#endif
return 0;
}
@@ -184,7 +197,11 @@ static u8 versal_net_get_bootmode(void)
u8 bootmode;
u32 reg = 0;
- reg = readl(&crp_base->boot_mode_usr);
+ if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) {
+ reg = zynqmp_pm_get_bootmode_reg();
+ } else {
+ reg = readl(&crp_base->boot_mode_usr);
+ }
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;