Merge tag 'u-boot-imx-next-20240603' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/20956

- Support different RAM sizes on imx8m phycoce boards.
- Support new toradex variants.
- Support Samsung 4GB DDR and Realtek RTL8211E PHY on imx8mm-cl-iot-gate.
- Convert imx8mm-phycore and imx8mp-phycore boards to use OF_UPSTREAM.

13 files changed, 441 insertions, 81 deletions

diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
index 99d3bf3af3b..6a3d816a48a 100644
--- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
@@ -46,7 +46,9 @@ struct lpddr4_desc {
 static const struct lpddr4_desc lpddr4_array[] = {
 	{ .name = "Nanya",	.id = 0x05000010, .subind = 0xff,
 	  .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
-	{ .name = "Samsung",	.id = 0x01061010, .subind = 0xff,
+	{ .name = "Samsung",	.id = 0x01061010, .subind = 0x04,
+	  .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
+	{ .name = "Samsung",	.id = 0x01061010, .subind = 0x02,
 	  .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
 	{ .name = "Kingston",	.id = 0xff000010, .subind = 0x04,
 	  .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
index ba158734142..bda7aac5be4 100644
--- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
+++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
@@ -8,6 +8,7 @@
 #include <efi_loader.h>
 #include <env.h>
 #include <extension_board.h>
+#include <fdt_support.h>
 #include <hang.h>
 #include <i2c.h>
 #include <init.h>
@@ -30,6 +31,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static int fec_phyaddr = -1;
+
 #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
 struct efi_fw_image fw_images[] = {
 #if defined(CONFIG_TARGET_IMX8MM_CL_IOT_GATE)
@@ -109,10 +112,72 @@ static int setup_fec(void)
 	return 0;
 }
 
+#define FDT_PHYADDR "/soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@0"
+#define FLIP_32B(val) (((val >> 24) & 0xff) | ((val << 8) & 0xff0000) | ((val >> 8) & 0xff00) | ((val << 24) & 0xff000000))
+static int fdt_set_fec_phy_addr(void *blob)
+{
+	u32 val;
+
+	if (fec_phyaddr < 0)
+		return -EINVAL;
+
+	val = FLIP_32B(fec_phyaddr);
+	return fdt_find_and_setprop(blob, FDT_PHYADDR, "reg", (const void *)&val,
+				    sizeof(val), 0);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	fdt_set_fec_phy_addr(blob);
+	return 0;
+}
+
+/*
+ * These are specific ID, purposed to distiguish between PHY vendors.
+ * These values are not equal to real vendors' OUI (half of MAC address)
+ */
+#define OUI_PHY_ATHEROS 0x1374
+#define OUI_PHY_REALTEK 0x0732
+
 int board_phy_config(struct phy_device *phydev)
 {
-	if (IS_ENABLED(CONFIG_FEC_MXC)) {
+	unsigned int model, rev, oui;
+	int phyid1, phyid2;
+	unsigned int reg;
+
+	if (!IS_ENABLED(CONFIG_FEC_MXC))
+		return 0;
+
+	phyid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1);
+	if (phyid1 < 0) {
+		printf("%s: PHYID1 registry read fail %i\n", __func__, phyid1);
+		return phyid1;
+	}
+
+	phyid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2);
+	if (phyid2 < 0) {
+		printf("%s: PHYID2 registry read fail %i\n", __func__, phyid2);
+		return phyid2;
+	}
+
+	reg = phyid2 | phyid1 << 16;
+	if (reg == 0xffff) {
+		printf("%s: There is no device @%i\n", __func__, phydev->addr);
+		return -ENODEV;
+	}
+
+	rev = reg & 0xf;
+	reg >>= 4;
+	model = reg & 0x3f;
+	reg >>= 6;
+	oui = reg;
+	debug("%s: PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
+	      __func__, phydev->addr, oui, model, rev);
+
+	switch (oui) {
+	case OUI_PHY_ATHEROS:
 		/* enable rgmii rxc skew and phy mode select to RGMII copper */
+		printf("phy: AR803x@%x\t", phydev->addr);
 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 
@@ -120,10 +185,45 @@ int board_phy_config(struct phy_device *phydev)
 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+		break;
+	case OUI_PHY_REALTEK:
+		printf("phy: RTL8211E@%x\t", phydev->addr);
+		/* RTL8211E-VB-CG - add TX and RX delay */
+		unsigned short val;
+
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x07);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0xa4);
+		val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c);
+		val |= (0x1 << 13) | (0x1 << 12) | (0x1 << 11);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val);
+		/* LEDs: set to extension page */
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0007);
+		/* extension Page44 */
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x002c);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x0430);//LCR
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1a, 0x0010);//LACR
+		/*
+		 * To disable EEE LED mode (blinking .4s/2s)
+		 * Extension Page5
+		 */
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0005);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x05, 0x8b82);//magic const
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x06, 0x052b);//magic const
+
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x00);// Back to Page0
 
-		if (phydev->drv->config)
-			phydev->drv->config(phydev);
+		break;
+	default:
+		printf("%s: ERROR: unknown PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
+		       __func__, phydev->addr, oui, model, rev);
+		return -ENOSYS;
 	}
+
+	fec_phyaddr = phydev->addr;
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
 	return 0;
 }
 
diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS
index e46e3691bac..58c5e2d0af9 100644
--- a/board/phytec/phycore_imx8mm/MAINTAINERS
+++ b/board/phytec/phycore_imx8mm/MAINTAINERS
@@ -2,10 +2,7 @@ phyCORE-i.MX8M Mini
 M:      Teresa Remmet <t.remmet@phytec.de>
 W:      https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/
 S:      Maintained
-F:      arch/arm/dts/imx8mm-phyboard-polis-rdk.dts
-F:      arch/arm/dts/imx8mm-phycore-som.dtsi
 F:      arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
-F:	arch/arm/dts/imx8mm-phygate-tauri-l.dts
 F:	arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi
 F:      board/phytec/phycore_imx8mm/
 F:	configs/imx8mm-phygate-tauri-l_defconfig
diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig
index f846d10bad9..bdf9e97beaa 100644
--- a/board/phytec/phycore_imx8mp/Kconfig
+++ b/board/phytec/phycore_imx8mp/Kconfig
@@ -12,5 +12,72 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg"
 
+config PHYCORE_IMX8MP_RAM_SIZE_FIX
+	bool "Set phyCORE-i.MX8MP RAM size fix instead of detecting"
+	default false
+	help
+	  RAM size is automatic being detected with the help of
+	  the EEPROM introspection data. Set RAM size to a fix value
+	  instead.
+
+choice
+	prompt "phyCORE-i.MX8MP RAM size"
+	depends on PHYCORE_IMX8MP_RAM_SIZE_FIX
+	default PHYCORE_IMX8MP_RAM_SIZE_2GB
+
+config PHYCORE_IMX8MP_RAM_SIZE_1GB
+	bool "1GB RAM"
+	help
+	  Set RAM size fix to 1GB for phyCORE-i.MX8MP.
+	  RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_2GB
+	bool "2GB RAM"
+	help
+	  Set RAM size fix to 2GB for phyCORE-i.MX8MP.
+	  RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_4GB
+	bool "4GB RAM"
+	help
+	  Set RAM size fix to 4GB for phyCORE-i.MX8MP.
+	  RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_8GB
+	bool "8GB RAM"
+	select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
+	help
+	  Set RAM size fix to 8GB for phyCORE-i.MX8MP.
+	  Only 2GHz RAMs are supported.
+
+endchoice
+
+config PHYCORE_IMX8MP_RAM_FREQ_FIX
+	bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting"
+	default false
+	help
+	  RAM frequency is automatic being detected with the help of
+	  the EEPROM introspection data. Set RAM frequency to a fix value
+	  instead.
+
+choice
+	prompt "phyCORE-i.MX8MP RAM frequency"
+	depends on PHYCORE_IMX8MP_RAM_FREQ_FIX
+	default PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS
+
+config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
+	bool "Use 2GHz RAM timings"
+	help
+	  Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of
+	  1.5GHz timings.
+
+config PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS
+	depends on !PHYCORE_IMX8MP_RAM_SIZE_8GB
+	bool "Use 1.5GHz RAM timings"
+	help
+	  Use fix 1.5GHz RAM timings for phyCORE-i.MX8MP instead of
+	  2GHz timings.
+endchoice
+
 source "board/phytec/common/Kconfig"
 endif
diff --git a/board/phytec/phycore_imx8mp/MAINTAINERS b/board/phytec/phycore_imx8mp/MAINTAINERS
index d3beb978d3a..645476ae30a 100644
--- a/board/phytec/phycore_imx8mp/MAINTAINERS
+++ b/board/phytec/phycore_imx8mp/MAINTAINERS
@@ -2,7 +2,6 @@ phyCORE-i.MX8M Plus
 M:      Teresa Remmet <t.remmet@phytec.de>
 W:      https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus/
 S:      Maintained
-F:      arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
 F:      arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
 F:      board/phytec/phycore_imx8mp/
 F:      configs/phycore-imx8mp_defconfig
diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c
index f2707b85960..9984b6c2601 100644
--- a/board/phytec/phycore_imx8mp/lpddr4_timing.c
+++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c
@@ -1839,3 +1839,156 @@ struct dram_timing_info dram_timing = {
 	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 3000, 400, 100, },
 };
+
+void set_dram_timings_2ghz_2gb(void)
+{
+	dram_timing.ddrc_cfg[3].val = 0x1323;
+	dram_timing.ddrc_cfg[4].val = 0x1e84800;
+	dram_timing.ddrc_cfg[5].val = 0x7a0118;
+	dram_timing.ddrc_cfg[8].val = 0xc00307a3;
+	dram_timing.ddrc_cfg[9].val = 0xc50000;
+	dram_timing.ddrc_cfg[10].val = 0xf4003f;
+	dram_timing.ddrc_cfg[11].val = 0xf30000;
+	dram_timing.ddrc_cfg[14].val = 0x2028222a;
+	dram_timing.ddrc_cfg[15].val = 0x8083f;
+	dram_timing.ddrc_cfg[16].val = 0xe0e000;
+	dram_timing.ddrc_cfg[17].val = 0x12040a12;
+	dram_timing.ddrc_cfg[18].val = 0x2050f0f;
+	dram_timing.ddrc_cfg[19].val = 0x1010009;
+	dram_timing.ddrc_cfg[20].val = 0x502;
+	dram_timing.ddrc_cfg[21].val = 0x20800;
+	dram_timing.ddrc_cfg[22].val = 0xe100002;
+	dram_timing.ddrc_cfg[23].val = 0x120;
+	dram_timing.ddrc_cfg[24].val = 0xc80064;
+	dram_timing.ddrc_cfg[25].val = 0x3e8001e;
+	dram_timing.ddrc_cfg[26].val = 0x3207a12;
+	dram_timing.ddrc_cfg[28].val = 0x4a3820e;
+	dram_timing.ddrc_cfg[30].val = 0x230e;
+	dram_timing.ddrc_cfg[37].val = 0x799;
+	dram_timing.ddrc_cfg[38].val = 0x9141d1c;
+	dram_timing.ddrc_cfg[74].val = 0x302;
+	dram_timing.ddrc_cfg[83].val = 0x599;
+	dram_timing.ddrc_cfg[99].val = 0x302;
+	dram_timing.ddrc_cfg[108].val = 0x599;
+	dram_timing.ddrphy_cfg[66].val = 0x18;
+	dram_timing.ddrphy_cfg[75].val = 0x1e3;
+	dram_timing.ddrphy_cfg[77].val = 0x1e3;
+	dram_timing.ddrphy_cfg[79].val = 0x1e3;
+	dram_timing.ddrphy_cfg[145].val = 0x3e8;
+	dram_timing.fsp_msg[0].drate = 4000;
+	dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
+	dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
+	dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
+	dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
+	dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
+	dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
+	dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
+	dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
+	dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
+	dram_timing.fsp_msg[3].drate = 4000;
+	dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
+	dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
+	dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
+	dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
+	dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
+	dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
+	dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
+	dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
+	dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
+	dram_timing.ddrphy_pie[480].val = 0x465;
+	dram_timing.ddrphy_pie[481].val = 0xfa;
+	dram_timing.ddrphy_pie[482].val = 0x9c4;
+	dram_timing.fsp_table[0] = 4000;
+}
+
+void set_dram_timings_1_5ghz_1gb(void)
+{
+	dram_timing.ddrc_cfg[3].val = 0x1233;
+	dram_timing.ddrc_cfg[5].val = 0x5b0087;
+	dram_timing.ddrc_cfg[6].val = 0x61027f10;
+	dram_timing.ddrc_cfg[7].val = 0x7b0;
+	dram_timing.ddrc_cfg[11].val = 0xf30000;
+	dram_timing.ddrc_cfg[23].val = 0x8d;
+	dram_timing.ddrc_cfg[45].val = 0xf070707;
+	dram_timing.ddrc_cfg[59].val = 0x1031;
+	dram_timing.ddrc_cfg[62].val = 0xc0012;
+	dram_timing.ddrc_cfg[77].val = 0x13;
+	dram_timing.ddrc_cfg[84].val = 0x1031;
+	dram_timing.ddrc_cfg[87].val = 0x30005;
+	dram_timing.ddrc_cfg[102].val = 0x5;
+	dram_timing.ddrphy_cfg[75].val = 0x1e3;
+	dram_timing.ddrphy_cfg[77].val = 0x1e3;
+	dram_timing.ddrphy_cfg[79].val = 0x1e3;
+	dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
+	dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
+	dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf32d;
+	dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf32d;
+	dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
+	dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
+	dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf32d;
+	dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf32d;
+}
+
+void set_dram_timings_2ghz_1gb(void)
+{
+	set_dram_timings_2ghz_2gb();
+	dram_timing.ddrc_cfg[5].val = 0x7a00b4;
+	dram_timing.ddrc_cfg[23].val = 0xbc;
+	dram_timing.ddrc_cfg[45].val = 0xf070707;
+	dram_timing.ddrc_cfg[62].val = 0xc0012;
+	dram_timing.ddrc_cfg[77].val = 0x13;
+	dram_timing.ddrc_cfg[87].val = 0x30005;
+	dram_timing.ddrc_cfg[102].val = 0x5;
+}
+
+void set_dram_timings_1_5ghz_4gb(void)
+{
+	dram_timing.ddrc_cfg[2].val = 0xa3080020;
+	dram_timing.ddrc_cfg[39].val = 0x17;
+	dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+	dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+	dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+	dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+	dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+	dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+	dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+	dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}
+
+void set_dram_timings_2ghz_4gb(void)
+{
+	set_dram_timings_2ghz_2gb();
+	dram_timing.ddrc_cfg[2].val = 0xa3080020;
+	dram_timing.ddrc_cfg[39].val = 0x17;
+	dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+	dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+	dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+	dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+	dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+	dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+	dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+	dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}
+
+void set_dram_timings_2ghz_8gb(void)
+{
+	set_dram_timings_2ghz_2gb();
+	dram_timing.ddrc_cfg[2].val = 0xa3080020;
+	dram_timing.ddrc_cfg[5].val = 0x7a017c;
+	dram_timing.ddrc_cfg[23].val = 0x184;
+	dram_timing.ddrc_cfg[39].val = 0x18;
+	dram_timing.ddrc_cfg[46].val = 0xf07;
+	dram_timing.ddrc_cfg[62].val = 0xc0026;
+	dram_timing.ddrc_cfg[77].val = 0x27;
+	dram_timing.ddrc_cfg[87].val = 0x3000a;
+	dram_timing.ddrc_cfg[102].val = 0xa;
+
+	dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310;
+	dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3;
+	dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310;
+	dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3;
+	dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310;
+	dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3;
+	dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310;
+	dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3;
+}
diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.h b/board/phytec/phycore_imx8mp/lpddr4_timing.h
new file mode 100644
index 00000000000..1c10e085a92
--- /dev/null
+++ b/board/phytec/phycore_imx8mp/lpddr4_timing.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+void set_dram_timings_2ghz_2gb(void);
+void set_dram_timings_2ghz_1gb(void);
+void set_dram_timings_2ghz_4gb(void);
+void set_dram_timings_1_5ghz_1gb(void);
+void set_dram_timings_1_5ghz_4gb(void);
+void set_dram_timings_2ghz_8gb(void);
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
index 35683591433..ef951361844 100644
--- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
+++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -9,6 +9,7 @@
 #include <asm/io.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <env.h>
+#include <init.h>
 #include <miiphy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -55,3 +56,13 @@ int board_late_init(void)
 
 	return 0;
 }
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+	if (!size)
+		return -EINVAL;
+
+	*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
+
+	return 0;
+}
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
index 352f803e454..0610d8bbd0b 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -20,95 +20,103 @@
 #include <power/pca9450.h>
 #include <spl.h>
 
+#include "lpddr4_timing.h"
 #include "../common/imx8m_som_detection.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define EEPROM_ADDR             0x51
-#define EEPROM_ADDR_FALLBACK    0x59
+#define EEPROM_ADDR		0x51
+#define EEPROM_ADDR_FALLBACK	0x59
 
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
 	return BOOT_DEVICE_BOOTROM;
 }
 
+enum phytec_imx8mp_ddr_eeprom_code {
+	PHYTEC_IMX8MP_DDR_1GB = 2,
+	PHYTEC_IMX8MP_DDR_2GB = 3,
+	PHYTEC_IMX8MP_DDR_4GB = 5,
+	PHYTEC_IMX8MP_DDR_8GB = 7,
+	PHYTEC_IMX8MP_DDR_4GB_2GHZ = 8,
+};
+
 void spl_dram_init(void)
 {
 	int ret;
+	bool use_2ghz_timings = false;
+	enum phytec_imx8mp_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL;
 
 	ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
 						EEPROM_ADDR_FALLBACK);
-	if (ret)
+	if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX))
 		goto out;
 
 	ret = phytec_imx8m_detect(NULL);
 	if (!ret)
 		phytec_print_som_info(NULL);
 
-	u8 rev = phytec_get_rev(NULL);
-	u8 somtype = phytec_get_som_type(NULL);
-
-	if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) {
-		dram_timing.ddrc_cfg[3].val = 0x1323;
-		dram_timing.ddrc_cfg[4].val = 0x1e84800;
-		dram_timing.ddrc_cfg[5].val = 0x7a0118;
-		dram_timing.ddrc_cfg[8].val = 0xc00307a3;
-		dram_timing.ddrc_cfg[9].val = 0xc50000;
-		dram_timing.ddrc_cfg[10].val = 0xf4003f;
-		dram_timing.ddrc_cfg[11].val = 0xf30000;
-		dram_timing.ddrc_cfg[14].val = 0x2028222a;
-		dram_timing.ddrc_cfg[15].val = 0x8083f;
-		dram_timing.ddrc_cfg[16].val = 0xe0e000;
-		dram_timing.ddrc_cfg[17].val = 0x12040a12;
-		dram_timing.ddrc_cfg[18].val = 0x2050f0f;
-		dram_timing.ddrc_cfg[19].val = 0x1010009;
-		dram_timing.ddrc_cfg[20].val = 0x502;
-		dram_timing.ddrc_cfg[21].val = 0x20800;
-		dram_timing.ddrc_cfg[22].val = 0xe100002;
-		dram_timing.ddrc_cfg[23].val = 0x120;
-		dram_timing.ddrc_cfg[24].val = 0xc80064;
-		dram_timing.ddrc_cfg[25].val = 0x3e8001e;
-		dram_timing.ddrc_cfg[26].val = 0x3207a12;
-		dram_timing.ddrc_cfg[28].val = 0x4a3820e;
-		dram_timing.ddrc_cfg[30].val = 0x230e;
-		dram_timing.ddrc_cfg[37].val = 0x799;
-		dram_timing.ddrc_cfg[38].val = 0x9141d1c;
-		dram_timing.ddrc_cfg[74].val = 0x302;
-		dram_timing.ddrc_cfg[83].val = 0x599;
-		dram_timing.ddrc_cfg[99].val = 0x302;
-		dram_timing.ddrc_cfg[108].val = 0x599;
-		dram_timing.ddrphy_cfg[66].val = 0x18;
-		dram_timing.ddrphy_cfg[75].val = 0x1e3;
-		dram_timing.ddrphy_cfg[77].val = 0x1e3;
-		dram_timing.ddrphy_cfg[79].val = 0x1e3;
-		dram_timing.ddrphy_cfg[145].val = 0x3e8;
-		dram_timing.fsp_msg[0].drate = 4000;
-		dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
-		dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
-		dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
-		dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
-		dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
-		dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
-		dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
-		dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
-		dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
-		dram_timing.fsp_msg[3].drate = 4000;
-		dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
-		dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
-		dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
-		dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
-		dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
-		dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
-		dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
-		dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
-		dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
-		dram_timing.ddrphy_pie[480].val = 0x465;
-		dram_timing.ddrphy_pie[481].val = 0xfa;
-		dram_timing.ddrphy_pie[482].val = 0x9c4;
-		dram_timing.fsp_table[0] = 4000;
+	if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) {
+		if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB))
+			size = PHYTEC_IMX8MP_DDR_1GB;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB))
+			size = PHYTEC_IMX8MP_DDR_2GB;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB))
+			size = PHYTEC_IMX8MP_DDR_4GB;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB))
+			size = PHYTEC_IMX8MP_DDR_8GB;
+	} else {
+		size = phytec_get_imx8m_ddr_size(NULL);
+	}
+
+	if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_FREQ_FIX)) {
+		if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) {
+			if (size == PHYTEC_IMX8MP_DDR_4GB)
+				size = PHYTEC_IMX8MP_DDR_4GB_2GHZ;
+			else
+				use_2ghz_timings = true;
+		} else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS)) {
+			if (size == PHYTEC_IMX8MP_DDR_4GB_2GHZ)
+				size = PHYTEC_IMX8MP_DDR_4GB;
+			else
+				use_2ghz_timings = false;
+		}
+	} else {
+		u8 rev = phytec_get_rev(NULL);
+		u8 somtype = phytec_get_som_type(NULL);
+
+		if (rev != PHYTEC_EEPROM_INVAL &&
+		    (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1)))
+			use_2ghz_timings = true;
 	}
 
+	switch (size) {
+	case PHYTEC_IMX8MP_DDR_1GB:
+		if (use_2ghz_timings)
+			set_dram_timings_2ghz_1gb();
+		else
+			set_dram_timings_1_5ghz_1gb();
+		break;
+	case PHYTEC_IMX8MP_DDR_2GB:
+		if (use_2ghz_timings)
+			set_dram_timings_2ghz_2gb();
+		break;
+	case PHYTEC_IMX8MP_DDR_4GB:
+		set_dram_timings_1_5ghz_4gb();
+		break;
+	case PHYTEC_IMX8MP_DDR_4GB_2GHZ:
+		set_dram_timings_2ghz_4gb();
+		break;
+	case PHYTEC_IMX8MP_DDR_8GB:
+		set_dram_timings_2ghz_8gb();
+		break;
+	default:
+		goto out;
+	}
+	ddr_init(&dram_timing);
+	return;
 out:
+	printf("Could not detect correct RAM size. Fallback to default.\n");
 	ddr_init(&dram_timing);
 }
 
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index 2225cefec16..a6e3c6afae8 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -158,6 +158,9 @@ const struct toradex_som toradex_modules[] = {
 	[85] = { "Apalis iMX6Q 2GB IT",                  TARGET_IS_ENABLED(APALIS_IMX6)     },
 	[86] = { "Verdin iMX8M Mini DualLite 2GB IT",    TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
 	[87] = { "Verdin iMX8M Mini Quad 2GB IT",        TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
+	[88] = { "Aquila AM69 Octa 32GB WB IT",          TARGET_IS_ENABLED(AQUILA_AM69_A72) },
+	[89] = { "Verdin iMX95 Hexa 16GB WB IT",         TARGET_IS_ENABLED(VERDIN_IMX95)    },
+	[90] = { "Verdin iMX8M Mini Quad 4GB WB ET",     TARGET_IS_ENABLED(VERDIN_IMX8MM)   },
 };
 
 struct pid4list {
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index 183ee0f2dc9..0d6dd1c3a72 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -113,6 +113,9 @@ enum {
 	APALIS_IMX6Q_IT_NOWINCE, /* 85 */
 	VERDIN_IMX8MMDL_2G_IT,
 	VERDIN_IMX8MMQ_2G_IT_NO_CAN,
+	AQUILA_AM69O_32G_WIFI_BT_IT,
+	VERDIN_IMX95H_16G_WIFI_BT_IT,
+	VERDIN_IMX8MMQ_4G_WIFI_BT_ET, /* 90 */
 };
 
 enum {
diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c b/board/toradex/verdin-imx8mm/lpddr4_timing.c
index 4dfec679b11..eece226b513 100644
--- a/board/toradex/verdin-imx8mm/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c
@@ -18,7 +18,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d400000, 0xa1080020},
 	{0x3d400020, 0x202},
 	{0x3d400024, 0x3a980},
-	{0x3d400064, 0x2d00d2},
+	{0x3d400064, 0x2d011d},
 	{0x3d4000d0, 0xc00305ba},
 	{0x3d4000d4, 0x940000},
 	{0x3d4000dc, 0xd4002d},
@@ -34,7 +34,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d40011c, 0x402},
 	{0x3d400130, 0x20600},
 	{0x3d400134, 0xc100002},
-	{0x3d400138, 0xd8},
+	{0x3d400138, 0x123},
 	{0x3d400144, 0x96004b},
 	{0x3d400180, 0x2ee0017},
 	{0x3d400184, 0x2605b8e},
@@ -56,7 +56,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d400204, 0x80808},
 	{0x3d400214, 0x7070707},
 	{0x3d400218, 0x7070707},
-	{0x3d40021c, 0xf0f},
+	{0x3d40021c, 0xf07},
 	{0x3d400250, 0x29001701},
 	{0x3d400254, 0x2c},
 	{0x3d40025c, 0x4000030},
@@ -71,7 +71,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d402020, 0x0},
 	{0x3d402024, 0x7d00},
 	{0x3d402050, 0x20d040},
-	{0x3d402064, 0x6001c},
+	{0x3d402064, 0x60026},
 	{0x3d4020dc, 0x840000},
 	{0x3d4020e0, 0x310000},
 	{0x3d4020e8, 0x66004d},
@@ -86,7 +86,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d40211c, 0x302},
 	{0x3d402130, 0x20300},
 	{0x3d402134, 0xa100002},
-	{0x3d402138, 0x1d},
+	{0x3d402138, 0x27},
 	{0x3d402144, 0x14000a},
 	{0x3d402180, 0x640004},
 	{0x3d402190, 0x3818200},
@@ -96,7 +96,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d403020, 0x0},
 	{0x3d403024, 0x1f40},
 	{0x3d403050, 0x20d040},
-	{0x3d403064, 0x30007},
+	{0x3d403064, 0x3000A},
 	{0x3d4030dc, 0x840000},
 	{0x3d4030e0, 0x310000},
 	{0x3d4030e8, 0x66004d},
@@ -111,7 +111,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{0x3d40311c, 0x302},
 	{0x3d403130, 0x20300},
 	{0x3d403134, 0xa100002},
-	{0x3d403138, 0x8},
+	{0x3d403138, 0xA},
 	{0x3d403144, 0x50003},
 	{0x3d403180, 0x190004},
 	{0x3d403190, 0x3818200},
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 020ee677480..4230f417d19 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -84,7 +84,8 @@ static void select_dt_from_module_version(void)
 		 */
 		is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) ||
 			  (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) ||
-			  (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN);
+			  (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN) ||
+			  (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET);
 	}
 
 	switch (get_pcb_revision()) {
@@ -117,7 +118,7 @@ int board_phys_sdram_size(phys_size_t *size)
 	if (!size)
 		return -EINVAL;
 
-	*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+	*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
 
 	return 0;
 }