Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:

	board/davinci/da830evm/da830evm.c
	board/edb93xx/sdram_cfg.c
	board/esd/otc570/otc570.c
	board/netstar/eeprom.c
	board/netstar/eeprom_start.S
	cpu/arm920t/ep93xx/timer.c
	include/configs/netstar.h
	include/configs/otc570.h

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

53 files changed, 2561 insertions, 2240 deletions

diff --git a/board/BuS/eb_cpux9k2/Makefile b/board/BuS/eb_cpux9k2/Makefile
new file mode 100644
index 00000000000..8171a7d0b51
--- /dev/null
+++ b/board/BuS/eb_cpux9k2/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= cpux9k2.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/BuS/eb_cpux9k2/config.mk b/board/BuS/eb_cpux9k2/config.mk
new file mode 100644
index 00000000000..ff2cfd170bb
--- /dev/null
+++ b/board/BuS/eb_cpux9k2/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x23f00000
diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c
new file mode 100644
index 00000000000..1f222756c84
--- /dev/null
+++ b/board/BuS/eb_cpux9k2/cpux9k2.c
@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2008-2009
+ * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
+ * Jens Scharsig <esw@bus-elektronik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <exports.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_mc.h>
+
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+
+#ifdef CONFIG_VIDEO
+#include <bus_vcxk.h>
+
+extern unsigned long display_width;
+extern unsigned long display_height;
+#endif
+
+#ifdef CONFIG_CMD_NAND
+void cpux9k2_nand_hw_init(void);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	at91_pio_t *pio	= (at91_pio_t *) AT91_PIO_BASE;
+	/* Enable Ctrlc */
+	console_init_f();
+
+	/* Correct IRDA resistor problem / Set PA23_TXD in Output */
+	writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
+
+	gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_STATUS_LED
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+#ifdef CONFIG_CMD_NAND
+	cpux9k2_nand_hw_init();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+
+int misc_init_r(void)
+{
+	uchar	mac[8];
+	uchar	tm;
+	uchar	midx;
+	uchar	macn6, macn7;
+
+#ifdef CONFIG_NET_MULTI
+	if (getenv("ethaddr") == NULL) {
+		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00,
+				CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+				(uchar *) &mac, sizeof(mac)) != 0) {
+			puts("Error reading MAC from EEPROM\n");
+		} else {
+			tm = 0;
+			macn6 = 0;
+			macn7 = 0xFF;
+			for (midx = 0; midx < 6; midx++) {
+				if ((mac[midx] != 0) && (mac[midx] != 0xFF))
+					tm++;
+				macn6 += mac[midx];
+				macn7 ^= mac[midx];
+			}
+			if ((macn6 != mac[6]) || (macn7 != mac[7]))
+				tm = 0;
+			if (tm)
+				eth_setenv_enetaddr("ethaddr", mac);
+			 else
+				puts("Error: invalid MAC at EEPROM\n");
+		}
+	}
+#endif
+	gd->jt[XF_do_reset] = (void *) do_reset;
+
+#ifdef CONFIG_STATUS_LED
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
+#endif
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+	udelay(10000);
+	eth_init(gd->bd);
+}
+#endif
+
+/*
+ * DRAM initialisations
+ */
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size =
+		get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE);
+	return 0;
+}
+
+/*
+ * Ethernet initialisations
+ */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, (u32) AT91_EMAC_BASE);
+	return rc;
+}
+#endif
+
+/*
+ * Disk On Chip (NAND) Millenium initialization.
+ * The NAND lives in the CS2* space
+ */
+#if defined(CONFIG_CMD_NAND)
+
+#define	MASK_ALE	(1 << 22)	/* our ALE is AD22 */
+#define	MASK_CLE	(1 << 21)	/* our CLE is AD21 */
+
+void cpux9k2_nand_hw_init(void)
+{
+	unsigned long csr;
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+	at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
+
+	/* Setup Smart Media, fitst enable the address range of CS3 */
+	writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa);
+
+	/* RWH = 1 | RWS = 0 | TDF = 1 | NWS = 3 */
+	csr =	AT91_SMC_CSR_RWHOLD(1) | AT91_SMC_CSR_TDF(1) |
+		AT91_SMC_CSR_NWS(3) |
+		AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_8 |
+		AT91_SMC_CSR_WSEN;
+	writel(csr, &mc->smc.csr[3]);
+
+	writel(AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, &pio->pioc.asr);
+	writel(AT91_PMX_CA_BFCK | AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE,
+		&pio->pioc.pdr);
+
+	/* Configure PC2 as input (signal Nand READY ) */
+	writel(AT91_PMX_CA_BFAVD, &pio->pioc.per);
+	writel(AT91_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
+	writel(AT91_PMX_CA_BFCK, &pio->pioc.codr);
+
+	/* PIOC clock enabling */
+	writel(1 << AT91_ID_PIOC, &pmc->pcer);
+}
+
+static void board_nand_hwcontrol(struct mtd_info *mtd,
+	int cmd, unsigned int ctrl)
+{
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	struct nand_chip *this = mtd->priv;
+	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= MASK_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= MASK_ALE;
+
+		if ((ctrl & NAND_NCE))
+			writel(1, &pio->pioc.codr);
+		else
+			writel(1, &pio->pioc.sodr);
+
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
+	}
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+static int board_nand_dev_ready(struct mtd_info *mtd)
+{
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	cpux9k2_nand_hw_init();
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = board_nand_hwcontrol;
+	nand->dev_ready = board_nand_dev_ready;
+	nand->chip_delay = 20;
+	return 0;
+}
+
+#endif
+
+#if defined(CONFIG_VIDEO)
+/*
+ * drv_video_init
+ * FUNCTION: initialize VCxK device
+ */
+
+int drv_video_init(void)
+{
+#ifdef CONFIG_SPLASH_SCREEN
+	unsigned long splash;
+#endif
+	char *s;
+	unsigned long csr;
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+	at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE;
+
+	printf("Init Video as ");
+	s = getenv("displaywidth");
+	if (s != NULL)
+		display_width = simple_strtoul(s, NULL, 10);
+	else
+		display_width = 256;
+	s = getenv("displayheight");
+	if (s != NULL)
+		display_height = simple_strtoul(s, NULL, 10);
+	else
+		display_height = 256;
+	printf("%ld x %ld pixel matrix\n", display_width, display_height);
+
+	/* RWH = 7 | RWS =7  | TDF = 15 | NWS = 0x7F */
+	csr =	AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) |
+		AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) |
+		AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
+		AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
+	writel(csr, &mc->smc.csr[2]);
+	writel(1 << AT91_ID_PIOB, &pmc->pcer);
+
+	vcxk_init(display_width, display_height);
+#ifdef CONFIG_SPLASH_SCREEN
+	s = getenv("splashimage");
+	if (s != NULL) {
+		splash = simple_strtoul(s, NULL, 16);
+		printf("use splashimage: %lx\n", splash);
+		video_display_bitmap(splash, 0, 0);
+	}
+#endif
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SOFT_I2C
+
+void i2c_init_board(void)
+{
+	u32 pin;
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+
+	writel(1 << AT91_ID_PIOA, &pmc->pcer);
+	pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
+	writel(pin, &pio->pioa.idr);
+	writel(pin, &pio->pioa.pudr);
+	writel(pin, &pio->pioa.per);
+	writel(pin, &pio->pioa.oer);
+	writel(pin, &pio->pioa.sodr);
+}
+
+#endif
+
+/*--------------------------------------------------------------------------*/
+
+#ifdef CONFIG_STATUS_LED
+
+void __led_toggle(led_id_t mask)
+{
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+
+	if (readl(&pio->piod.odsr) & mask)
+		writel(mask, &pio->piod.codr);
+	else
+		writel(mask, &pio->piod.codr);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+
+	writel(1 << AT91_ID_PIOD, &pmc->pcer);	/* Enable PIOB clock */
+	/* Disable peripherals on LEDs */
+	writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per);
+	/* Enable pins as outputs */
+	writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.oer);
+	/* Turn all LEDs OFF */
+	writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.sodr);
+
+	__led_set(mask, state);
+}
+
+void __led_set(led_id_t mask, int state)
+{
+	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+	if (state == STATUS_LED_ON)
+		writel(mask, &pio->piod.codr);
+	else
+		writel(mask, &pio->piod.sodr);
+}
+
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int rcode = 0;
+	ulong side;
+	ulong bright;
+
+	switch (argc) {
+	case 3:
+		side = simple_strtoul(argv[1], NULL, 10);
+		bright = simple_strtoul(argv[2], NULL, 10);
+		if ((side >= 0) && (side <= 3) &&
+				(bright >= 0) && (bright <= 1000)) {
+			vcxk_setbrightness(side, bright);
+			rcode = 0;
+		} else {
+			printf("parameters out of range\n");
+			printf("Usage:\n%s\n", cmdtp->usage);
+			rcode = 1;
+		}
+		break;
+	default:
+		printf("Usage:\n%s\n", cmdtp->usage);
+		rcode = 1;
+		break;
+	}
+	return rcode;
+}
+
+/*---------------------------------------------------------------------------*/
+
+U_BOOT_CMD(
+	bright,	3,	0,	do_brightness,
+	"bright  - sets the display brightness\n",
+	" <side> <0..1000>\n        side: 0/3=both; 1=first; 2=second\n"
+);
+
+/* EOF cpu9k2.c */
diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c
index 9f73df69033..258d1eac292 100644
--- a/board/atmel/at91cap9adk/at91cap9adk.c
+++ b/board/atmel/at91cap9adk/at91cap9adk.c
@@ -282,7 +282,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2008 ATMEL Corp\n");
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
-		AT91_CPU_NAME,
+		CONFIG_SYS_AT91_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
diff --git a/board/atmel/at91rm9200dk/at91rm9200dk.c b/board/atmel/at91rm9200dk/at91rm9200dk.c
index c761dd7467d..49b5fe3203d 100644
--- a/board/atmel/at91rm9200dk/at91rm9200dk.c
+++ b/board/atmel/at91rm9200dk/at91rm9200dk.c
@@ -23,9 +23,15 @@
  */
 
 #include <common.h>
+#include <exports.h>
+#include <netdev.h>
 #include <asm/arch/AT91RM9200.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_DRIVER_ETHER)
 #include <at91rm9200_net.h>
 #include <dm9161.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -95,6 +101,15 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
 #endif
 #endif	/* CONFIG_DRIVER_ETHER */
 
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
+
 /*
  * Disk On Chip (NAND) Millenium initialization.
  * The NAND lives in the CS2* space
diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c
index ea684e949d0..570a09a0741 100644
--- a/board/atmel/at91rm9200ek/at91rm9200ek.c
+++ b/board/atmel/at91rm9200ek/at91rm9200ek.c
@@ -23,9 +23,14 @@
  */
 
 #include <common.h>
+#include <exports.h>
+#include <netdev.h>
 #include <asm/arch/AT91RM9200.h>
+#include <asm/io.h>
+#if defined(CONFIG_DRIVER_ETHER)
 #include <at91rm9200_net.h>
 #include <dm9161.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -84,3 +89,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
 	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
 }
 #endif
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 7ead2b8977c..de5cfaeb00a 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -217,7 +217,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2008 ATMEL Corp\n");
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
-		AT91_CPU_NAME,
+		CONFIG_SYS_AT91_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 0b7065b715d..5cd7aa75f8f 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -25,13 +25,13 @@
 #include <common.h>
 #include <asm/sizes.h>
 #include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91sam9263_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
 #include <asm/arch/hardware.h>
 #include <lcd.h>
@@ -52,49 +52,57 @@ DECLARE_GLOBAL_DATA_PTR;
 static void at91sam9263ek_nand_hw_init(void)
 {
 	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC0_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
 
 	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
-	at91_sys_write(AT91_MATRIX_EBI0CSA,
-		       csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
-		       AT91_SMC_DBW_16 |
+		       AT91_SMC_MODE_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
-		       AT91_SMC_DBW_8 |
+		       AT91_SMC_MODE_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(2));
+		       AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
 
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
-				      1 << AT91SAM9263_ID_PIOCDE);
+	writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE,
+		&pmc->pcer);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
 #ifdef CONFIG_MACB
 static void at91sam9263ek_macb_hw_init(void)
 {
-	unsigned long rstc;
-
+	unsigned long 	erstl;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pio_t	*pio	= (at91_pio_t *) AT91_PIO_BASE;
+	at91_rstc_t	*rstc	= (at91_rstc_t *) AT91_RSTC_BASE;
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+	writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
 
 	/*
 	 * Disable pull-up on:
@@ -104,35 +112,27 @@ static void at91sam9263ek_macb_hw_init(void)
 	 *
 	 * PHY has internal pull-down
 	 */
-	writel(pin_to_mask(AT91_PIN_PC25),
-	       pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
-	writel(pin_to_mask(AT91_PIN_PE25) |
-	       pin_to_mask(AT91_PIN_PE26),
-	       pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
 
-	rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+	writel(1 << 25, &pio->pioc.pudr);
+	writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
 
-	/* Need to reset PHY -> 500ms reset */
-	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
-				     AT91_RSTC_URSTEN);
+	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
 
-	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+	/* Need to reset PHY -> 500ms reset */
+	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
+		AT91_RSTC_MR_URSTEN, &rstc->mr);
 
+	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 	/* Wait for end hardware reset */
-	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+		;
 
 	/* Restore NRST value */
-	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     (rstc) |
-				     AT91_RSTC_URSTEN);
+	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
 
 	/* Re-enable pull-up */
-	writel(pin_to_mask(AT91_PIN_PC25),
-	       pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
-	writel(pin_to_mask(AT91_PIN_PE25) |
-	       pin_to_mask(AT91_PIN_PE26),
-	       pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
+	writel(1 << 25, &pio->pioc.puer);
+	writel((1 << 25) | (1 <<26), &pio->pioe.puer);
 
 	at91_macb_hw_init();
 }
@@ -158,41 +158,42 @@ vidinfo_t panel_info = {
 
 void lcd_enable(void)
 {
-	at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power up */
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
 }
 
 void lcd_disable(void)
 {
-	at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power down */
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
 }
 
 static void at91sam9263ek_lcd_hw_init(void)
 {
-	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
-	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
-	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
-	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
-	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
-	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
-	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
-	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
-	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
-	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
-	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
-	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
-	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
-	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
-	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
-	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
-	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
-	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
-	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
-	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
-	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
-	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */
-
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
-
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
+	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
+
+	writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
 	gd->fb_base = AT91SAM9263_SRAM0_BASE;
 }
 
@@ -217,7 +218,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2008 ATMEL Corp\n");
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
-		AT91_CPU_NAME,
+		CONFIG_SYS_AT91_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
@@ -258,7 +259,7 @@ int board_init(void)
 	at91sam9263ek_nand_hw_init();
 #endif
 #ifdef CONFIG_HAS_DATAFLASH
-	at91_set_gpio_output(AT91_PIN_PE20, 1);	/* select spi0 clock */
+	at91_set_pio_output(AT91_PIO_PORTE, 20, 1);	/* select spi0 clock */
 	at91_spi0_hw_init(1 << 0);
 #endif
 #ifdef CONFIG_MACB
@@ -297,7 +298,7 @@ int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
 #ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
+	rc = macb_eth_initialize(0, (void *) AT91_EMAC_BASE, 0x00);
 #endif
 	return rc;
 }
diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c
index 82c53886434..fa1f05b0de1 100644
--- a/board/atmel/at91sam9263ek/led.c
+++ b/board/atmel/at91sam9263ek/led.c
@@ -23,22 +23,25 @@
  */
 
 #include <common.h>
-#include <asm/arch/at91sam9263.h>
+#include <asm/arch/hardware.h>
 #include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
 
 void coloured_LED_init(void)
 {
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
-				      1 << AT91SAM9263_ID_PIOCDE);
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
-	at91_set_gpio_output(CONFIG_RED_LED, 1);
-	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
-	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+	writel(1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE,
+		&pmc->pcer);
 
-	at91_set_gpio_value(CONFIG_RED_LED, 0);
-	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+	at91_set_pio_output(CONFIG_RED_LED, 1);
+	at91_set_pio_output(CONFIG_GREEN_LED, 1);
+	at91_set_pio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_pio_value(CONFIG_RED_LED, 0);
+	at91_set_pio_value(CONFIG_GREEN_LED, 1);
+	at91_set_pio_value(CONFIG_YELLOW_LED, 1);
 }
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 45a14a95f26..edfb627bbcd 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -217,7 +217,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2008 ATMEL Corp\n");
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
-		AT91_CPU_NAME,
+		CONFIG_SYS_AT91_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index 7013ba2b132..e3749174681 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -157,7 +157,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2008 ATMEL Corp\n");
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
-		AT91_CPU_NAME,
+		CONFIG_SYS_AT91_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
diff --git a/board/cmc_pu2/cmc_pu2.c b/board/cmc_pu2/cmc_pu2.c
index 3ad756de1c8..0ac851c97f3 100644
--- a/board/cmc_pu2/cmc_pu2.c
+++ b/board/cmc_pu2/cmc_pu2.c
@@ -30,8 +30,12 @@
 #include <common.h>
 #include <asm/mach-types.h>
 #include <asm/arch/AT91RM9200.h>
+#include <asm/io.h>
+#include <netdev.h>
+#if defined(CONFIG_DRIVER_ETHER)
 #include <at91rm9200_net.h>
 #include <dm9161.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -177,3 +181,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
 
 #endif
 #endif	/* CONFIG_DRIVER_ETHER */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
diff --git a/board/csb637/csb637.c b/board/csb637/csb637.c
index fbc3c87c5da..d7fdcc4f739 100644
--- a/board/csb637/csb637.c
+++ b/board/csb637/csb637.c
@@ -23,8 +23,12 @@
 
 #include <common.h>
 #include <asm/arch/AT91RM9200.h>
+#include <netdev.h>
+#include <asm/io.h>
+#if defined(CONFIG_DRIVER_ETHER)
 #include <at91rm9200_net.h>
 #include <bcm5221.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -79,3 +83,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
 
 #endif
 #endif	/* CONFIG_DRIVER_ETHER */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da830evm/da830evm.c
index 12df1f81837..ed668afccc8 100644
--- a/board/davinci/da830evm/da830evm.c
+++ b/board/davinci/da830evm/da830evm.c
@@ -34,7 +34,11 @@
 
 #include <common.h>
 #include <i2c.h>
+#include <net.h>
+#include <netdev.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
 #include <asm/io.h>
 #include "../common/misc.h"
 
@@ -51,6 +55,37 @@ static const struct pinmux_config spi0_pins[] = {
 	{ pinmux[7], 1, 7 }
 };
 
+/* EMIF-A bus pins for 8-bit NAND support on CS3 */
+static const struct pinmux_config emifa_nand_pins[] = {
+	{ pinmux[13], 1, 6 },
+	{ pinmux[13], 1, 7 },
+	{ pinmux[14], 1, 0 },
+	{ pinmux[14], 1, 1 },
+	{ pinmux[14], 1, 2 },
+	{ pinmux[14], 1, 3 },
+	{ pinmux[14], 1, 4 },
+	{ pinmux[14], 1, 5 },
+	{ pinmux[15], 1, 7 },
+	{ pinmux[16], 1, 0 },
+	{ pinmux[18], 1, 1 },
+	{ pinmux[18], 1, 4 },
+	{ pinmux[18], 1, 5 },
+};
+
+/* EMAC PHY interface pins */
+static const struct pinmux_config emac_pins[] = {
+	{ pinmux[9], 0, 5 },
+	{ pinmux[10], 2, 1 },
+	{ pinmux[10], 2, 2 },
+	{ pinmux[10], 2, 3 },
+	{ pinmux[10], 2, 4 },
+	{ pinmux[10], 2, 5 },
+	{ pinmux[10], 2, 6 },
+	{ pinmux[10], 2, 7 },
+	{ pinmux[11], 2, 0 },
+	{ pinmux[11], 2, 1 },
+};
+
 /* UART pin muxer settings */
 static const struct pinmux_config uart_pins[] = {
 	{ pinmux[8], 2, 7 },
@@ -59,8 +94,8 @@ static const struct pinmux_config uart_pins[] = {
 
 /* I2C pin muxer settings */
 static const struct pinmux_config i2c_pins[] = {
-	{ pinmux[9], 2, 3 },
-	{ pinmux[9], 2, 4 }
+	{ pinmux[8], 2, 3 },
+	{ pinmux[8], 2, 4 }
 };
 
 /* USB0_DRVVBUS pin muxer settings */
@@ -77,6 +112,12 @@ static const struct pinmux_resource pinmuxes[] = {
 #ifdef CONFIG_USB_DA8XX
 	PINMUX_ITEM(usb_pins),
 #endif
+#ifdef CONFIG_USE_NAND
+	PINMUX_ITEM(emifa_nand_pins),
+#endif
+#if defined(CONFIG_DRIVER_TI_EMAC)
+	PINMUX_ITEM(emac_pins),
+#endif
 };
 
 int board_init(void)
@@ -96,6 +137,22 @@ int board_init(void)
 	writel(0xffffffff, &davinci_aintc_regs->ecr3);
 #endif
 
+#ifdef CONFIG_NAND_DAVINCI
+	/* EMIFA 100MHz clock select */
+	writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2,
+	       &davinci_syscfg_regs->cfgchip3);
+	/* NAND CS setup */
+	writel((DAVINCI_ABCR_WSETUP(0) |
+		DAVINCI_ABCR_WSTROBE(2) |
+		DAVINCI_ABCR_WHOLD(0) |
+		DAVINCI_ABCR_RSETUP(0) |
+		DAVINCI_ABCR_RSTROBE(2) |
+		DAVINCI_ABCR_RHOLD(0) |
+		DAVINCI_ABCR_TA(2) |
+		DAVINCI_ABCR_ASIZE_8BIT),
+	       &davinci_emif_regs->AB2CR);
+#endif
+
 	/* arch number of the board */
 	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
 
@@ -132,3 +189,44 @@ int board_init(void)
 
 	return(0);
 }
+
+#if defined(CONFIG_DRIVER_TI_EMAC)
+
+#define PHY_SW_I2C_ADDR	0x5f /* Address of PHY on i2c bus */
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+	u_int8_t mac_addr[6];
+	u_int8_t switch_start_cmd[2] = { 0x01, 0x23 };
+
+	/* Read Ethernet MAC address from EEPROM */
+	if (dvevm_read_mac_address(mac_addr))
+		/* set address env if not already set */
+		dv_configure_mac_address(mac_addr);
+
+	/* read the address back from env */
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr))
+		return -1;
+
+	/* provide the resulting addr to the driver */
+	davinci_eth_set_mac_addr(mac_addr);
+
+	/* enable the Ethernet switch in the 3 port PHY */
+	if (i2c_write(PHY_SW_I2C_ADDR, 0, 0,
+			switch_start_cmd, sizeof(switch_start_cmd))) {
+		printf("Ethernet switch start failed!\n");
+		return -1;
+	}
+
+	/* finally, initialise the driver */
+	if (!davinci_emac_initialize()) {
+		printf("Error: Ethernet init failed!\n");
+		return -1;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c
index 6155f0eb459..440ad11fcb0 100644
--- a/board/edb93xx/sdram_cfg.c
+++ b/board/edb93xx/sdram_cfg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
  *
  * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
  *
@@ -30,9 +30,9 @@
 		(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
 
 #define PRECHARGE_BANK(bank)		(*(volatile uint32_t *)		\
-				(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank))
+		(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0
 
-static void force_precharge(void);
+static void precharge_all_banks(void);
 static void setup_refresh_timer(void);
 static void program_mode_registers(void);
 
@@ -47,7 +47,7 @@ void sdram_cfg(void)
 
 	early_udelay(200);
 
-	force_precharge();
+	precharge_all_banks();
 
 	setup_refresh_timer();
 
@@ -57,19 +57,37 @@ void sdram_cfg(void)
 	writel(GLCONFIG_CKE, &sdram->glconfig);
 }
 
-static void force_precharge(void)
+static void precharge_all_banks(void)
 {
+	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+	/* Issue PRECHARGE ALL commands */
+	writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig);
+
 	/*
-	 * Errata most EP93xx revisions say that PRECHARGE ALL isn't always
-	 * issued.
+	 * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always
+	 * issued
 	 *
-	 * Do a read from each bank to make sure they're precharged
+	 * Cirrus proposes a workaround which consists in performing a read from
+	 * each bank to force the precharge. This causes some boards to hang.
+	 * Writing to the SDRAM banks instead of reading has the same
+	 * side-effect (the SDRAM controller issues the necessary precharges),
+	 * but is known to work on all supported boards
 	 */
 
 	PRECHARGE_BANK(0);
+
+#if (CONFIG_NR_DRAM_BANKS >= 2)
 	PRECHARGE_BANK(1);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS >= 3)
 	PRECHARGE_BANK(2);
+#endif
+
+#if (CONFIG_NR_DRAM_BANKS == 4)
 	PRECHARGE_BANK(3);
+#endif
 }
 
 static void setup_refresh_timer(void)
@@ -101,6 +119,11 @@ static void setup_refresh_timer(void)
 
 static void program_mode_registers(void)
 {
+	struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
+
+	/* Select mode register update mode */
+	writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
+
 	/*
 	 * The mode registers are programmed by performing a read from each
 	 * SDRAM bank. The value of the address that is read defines the value
diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c
index 056df37ce75..07d9c629773 100644
--- a/board/esd/otc570/otc570.c
+++ b/board/esd/otc570/otc570.c
@@ -28,13 +28,13 @@
 
 #include <common.h>
 #include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91sam9_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/io.h>
 #include <atmel_lcdc.h>
@@ -58,10 +58,10 @@ int get_hw_rev(void)
 	if (hw_rev >= 0)
 		return hw_rev;
 
-	hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
-	hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
-	hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
-	hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
+	hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
+	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
 
 	if (hw_rev == 15)
 		hw_rev = 0;
@@ -73,40 +73,44 @@ int get_hw_rev(void)
 static void otc570_nand_hw_init(void)
 {
 	unsigned long csa;
+	at91_smc_t 	*smc 	= (at91_smc_t *) AT91_SMC0_BASE;
+	at91_matrix_t 	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
 
 	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
-	at91_sys_write(AT91_MATRIX_EBI0CSA,
-		csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-		AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-		AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-	at91_sys_write(AT91_SMC_MODE(3),
-		AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		AT91_SMC_EXNWMODE_DISABLE |
-		AT91_SMC_DBW_8 |
-		AT91_SMC_TDF_(2));
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		       AT91_SMC_MODE_DBW_8 |
+		       AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif /* CONFIG_CMD_NAND */
 
 #ifdef CONFIG_MACB
 static void otc570_macb_hw_init(void)
 {
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+	writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
 	at91_macb_hw_init();
 }
 #endif
@@ -119,26 +123,27 @@ static void otc570_macb_hw_init(void)
  */
 static void otc570_ethercat_hw_init(void)
 {
+	at91_smc_t 	*smc1 	= (at91_smc_t *) AT91_SMC1_BASE;
+
 	/* Configure SMC EBI1_CS0 for EtherCAT */
-	at91_sys_write(AT91_SMC1_SETUP(0),
-		AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
-		AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC1_PULSE(0),
-		AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
-		AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(9));
-	at91_sys_write(AT91_SMC1_CYCLE(0),
-		AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(6));
+	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc1->cs[0].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
+		AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
+		&smc1->cs[0].pulse);
+	writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
+		&smc1->cs[0].cycle);
 	/*
 	 * Configure behavior at external wait signal, byte-select mode, 16 bit
 	 * data bus width, none data float wait states and TDF optimization
 	 */
-	at91_sys_write(AT91_SMC1_MODE(0),
-		AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
-		AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
-		AT91_SMC_TDFMODE);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
+		AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
+		AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_B_periph(AT91_PIN_PE20, 0);	/* EBI1_NWAIT */
+	at91_set_b_periph(AT91_PIO_PORTE, 20, 0);	/* EBI1_NWAIT */
 }
 
 #ifdef CONFIG_LCD
@@ -164,43 +169,44 @@ vidinfo_t panel_info = {
 
 void lcd_enable(void)
 {
-	at91_set_gpio_value(AT91_PIN_PA30, 0);	/* power up */
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power up */
 }
 
 void lcd_disable(void)
 {
-	at91_set_gpio_value(AT91_PIN_PA30, 1);	/* power down */
+	at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power down */
 }
 
 static void otc570_lcd_hw_init(void)
 {
-	at91_set_A_periph(AT91_PIN_PC0, 0);	/* LCDVSYNC */
-	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
-	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
-	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
-	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
-	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
-	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
-	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
-	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
-	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
-	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
-	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
-	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
-	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
-	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
-	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
-	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
-	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
-	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
-	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
-	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
-	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
-	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */
-	at91_set_gpio_output(AT91_PIN_PA30, 1);	/* PCI */
-
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
-
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
+	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
+	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
+	at91_set_pio_output(AT91_PIO_PORTA, 30, 1);	/* PCI */
+
+	writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
 	gd->fb_base = CONFIG_OTC570_LCD_BASE;
 }
 
@@ -219,7 +225,7 @@ void lcd_show_board_info(void)
 		nand_size += nand_info[i].size;
 
 	lcd_printf("\n%s\n", U_BOOT_VERSION);
-	lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME,
+	lcd_printf("%s CPU at %s MHz\n", CONFIG_SYS_AT91_CPU_NAME,
 					strmhz(temp, get_cpu_clk_rate()));
 	lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
@@ -242,7 +248,7 @@ int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
 #ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
+	rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00);
 #endif
 	return rc;
 }
@@ -290,32 +296,33 @@ u32 get_board_rev(void)
 #ifdef CONFIG_MISC_INIT_R
 int misc_init_r(void)
 {
-	char str[64];
+	char		str[64];
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
 
-	at91_set_gpio_output(AT91_PIN_PA29, 1);
-	at91_set_A_periph(AT91_PIN_PA26, 1);			/* TXD0 */
-	at91_set_A_periph(AT91_PIN_PA27, 0);			/* RXD0 */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
+	at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
+	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);	/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* RXD0 */
+	writel(1 << AT91SAM9263_ID_US0,	&pmc->pcer);
 	/* Set USART_MODE = 1 (RS485) */
-	at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1);
+	writel(1, 0xFFF8C004);
 
 	printf("USART0: ");
 
 	if (getenv_r("usart0", str, sizeof(str)) == -1) {
 		printf("No entry - assuming 1-wire\n");
 		/* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
-		at91_set_gpio_output(AT91_PIN_PA29, 0);
+		at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
 	} else {
 		if (strcmp(str, "1-wire") == 0) {
 			printf("%s\n", str);
-			at91_set_gpio_output(AT91_PIN_PA29, 0);
+			at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
 		} else if (strcmp(str, "rs485") == 0) {
 			printf("%s\n", str);
-			at91_set_gpio_output(AT91_PIN_PA29, 1);
+			at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
 		} else {
 			printf("Wrong entry - assuming 1-wire ");
 			printf("(valid values are '1-wire' or 'rs485')\n");
-			at91_set_gpio_output(AT91_PIN_PA29, 0);
+			at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
 		}
 	}
 	printf("Display memory address: 0x%08lX\n", gd->fb_base);
@@ -326,14 +333,17 @@ int misc_init_r(void)
 
 int board_init(void)
 {
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
 	/* Peripheral Clock Enable Register */
-	at91_sys_write(AT91_PMC_PCER,	1 << AT91SAM9263_ID_PIOA |
-					1 << AT91SAM9263_ID_PIOB |
-					1 << AT91SAM9263_ID_PIOCDE |
-					1 << AT91SAM9263_ID_TWI |
-					1 << AT91SAM9263_ID_SPI0 |
-					1 << AT91SAM9263_ID_LCDC |
-					1 << AT91SAM9263_ID_UHP);
+	writel(	1 << AT91SAM9263_ID_PIOA |
+		1 << AT91SAM9263_ID_PIOB |
+		1 << AT91SAM9263_ID_PIOCDE |
+		1 << AT91SAM9263_ID_TWI |
+		1 << AT91SAM9263_ID_SPI0 |
+		1 << AT91SAM9263_ID_LCDC |
+		1 << AT91SAM9263_ID_UHP,
+		&pmc->pcer);
 
 	/* arch number of OTC570-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_OTC570;
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index e385a78a2e8..0f7fa69a74c 100644
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -46,6 +46,34 @@ const unsigned char fpgadata[] =
  */
 #include "../common/fpga.c"
 
+/*
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
+ */
+void init_coupler(u32 addr)
+{
+	struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+
+	/* dominant */
+	out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+	out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+	out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+	      OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+	out_8(&ctrl->cr, 0x00);
+
+	/* delay */
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+}
+
 int board_early_init_f(void)
 {
 	/*
diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c
index 1a700b649cc..0017962d420 100644
--- a/board/eukrea/cpuat91/cpuat91.c
+++ b/board/eukrea/cpuat91/cpuat91.c
@@ -26,9 +26,14 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <asm/arch/AT91RM9200.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_DRIVER_ETHER)
 #include <at91rm9200_net.h>
 #include <ks8721.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -79,3 +84,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
 
 #endif	/* CONFIG_CMD_NET */
 #endif	/* CONFIG_DRIVER_ETHER */
+#ifdef CONFIG_DRIVER_AT91EMAC
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c
deleted file mode 100644
index 50d9748c71a..00000000000
--- a/board/exbitgen/exbitgen.c
+++ /dev/null
@@ -1,126 +0,0 @@
-#include <common.h>
-#include <asm/u-boot.h>
-#include <asm/processor.h>
-#include "exbitgen.h"
-
-void sdram_init(void);
-
-/* ************************************************************************ */
-int board_early_init_f (void)
-/* ------------------------------------------------------------------------ --
- * Purpose     :
- * Remarks     :
- * Restrictions:
- * See also    :
- * Example     :
- * ************************************************************************ */
-{
-	unsigned long i;
-
-   /*-------------------------------------------------------------------------+
-   | Interrupt controller setup for the Walnut board.
-   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
-   |       IRQ 16    405GP internally generated; active low; level sensitive
-   |       IRQ 17-24 RESERVED
-   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
-   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
-   |       IRQ 27 (EXT IRQ 2) Not Used
-   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
-   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
-   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
-   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
-   | Note for Walnut board:
-   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
-   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
-   |       interrupt. The FPGA must be read to determine which device
-   |       caused the interrupt. The default setting of the FPGA clears
-   |
-   +-------------------------------------------------------------------------*/
-
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr (UIC0CR, 0x00000020);	/* set all but FPGA SMI to be non-critical */
-	mtdcr (UIC0PR, 0xFFFFFF90);	/* set int polarities */
-	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
-	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	/* Perform reset of PHY connected to PPC via register in CPLD */
-	out8 (PHY_CTRL_ADDR, 0x2e);	/* activate nRESET,FDX,F100,ANEN, enable output */
-	for (i = 0; i < 10000000; i++) {
-		;
-	}
-	out8 (PHY_CTRL_ADDR, 0x2f);	/* deactivate nRESET */
-
-	return 0;
-}
-
-
-/* ************************************************************************ */
-int checkboard (void)
-/* ------------------------------------------------------------------------ --
- * Purpose     :
- * Remarks     :
- * Restrictions:
- * See also    :
- * Example     :
- * ************************************************************************ */
-{
-	printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR));
-	return (0);
-}
-
-/* ************************************************************************ */
-phys_size_t initdram (int board_type)
-/* ------------------------------------------------------------------------ --
- * Purpose     : Determines size of mounted DRAM.
- * Remarks     : Size is determined by reading SDRAM configuration registers as
- *               set up by sdram_init.
- * Restrictions:
- * See also    :
- * Example     :
- * ************************************************************************ */
-{
-	ulong tot_size;
-	ulong bank_size;
-	ulong tmp;
-
-	/*
-	 * ToDo: Move the asm init routine sdram_init() to this C file,
-	 * or even better use some common ppc4xx code available
-	 * in cpu/ppc4xx
-	 */
-	sdram_init();
-
-	tot_size = 0;
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	return tot_size;
-}
diff --git a/board/exbitgen/exbitgen.h b/board/exbitgen/exbitgen.h
deleted file mode 100644
index dceaf6dbc0c..00000000000
--- a/board/exbitgen/exbitgen.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#define GPIO_CPU_LED		GPIO_3
-
-
-#define CPLD_BASE		0x10000000		/* t.b.m. */
-#define DEBUG_LEDS_ADDR		CPLD_BASE + 0x01
-#define HW_ID_ADDR		CPLD_BASE + 0x02
-#define DIP_SWITCH_ADDR		CPLD_BASE + 0x04
-#define PHY_CTRL_ADDR		CPLD_BASE + 0x05
-#define SPI_OUT_ADDR		CPLD_BASE + 0x07
-#define SPI_IN_ADDR		CPLD_BASE + 0x08
-#define MDIO_OUT_ADDR		CPLD_BASE + 0x09
-#define MDIO_IN_ADDR		CPLD_BASE + 0x0A
-#define MISC_OUT_ADDR		CPLD_BASE + 0x0B
-
-/* Addresses used on I2C bus */
-#define LM75_CHIP_ADDR		0x9C
-#define LM75_CPU_ADDR		0x9E
-#define SDRAM_SPD_ADDR		0xA0
-
-#define SDRAM_SPD_WRITE_ADDRESS	(SDRAM_SPD_ADDR)
-#define SDRAM_SPD_READ_ADDRESS	(SDRAM_SPD_ADDR+1)
-
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#ifndef TRUE
-#define TRUE 1
-#endif
diff --git a/board/exbitgen/flash.c b/board/exbitgen/flash.c
deleted file mode 100644
index cd45cb697dd..00000000000
--- a/board/exbitgen/flash.c
+++ /dev/null
@@ -1,597 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <asm/processor.h>
-#include <ppc4xx.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-#ifdef MEIGSBOARD_ONBOARD_FLASH /* onboard = 2MB */
-#  ifdef CONFIG_EXBITGEN
-#     define FLASH_WORD_SIZE unsigned long
-#  endif
-#else /* Meigsboard socket flash = 512KB */
-#  ifdef CONFIG_EXBITGEN
-#    define FLASH_WORD_SIZE unsigned char
-#  endif
-#endif
-
-#ifdef CONFIG_EXBITGEN
-#define ADDR0           0x5555
-#define ADDR1           0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	unsigned long bank_size;
-	unsigned long tot_size;
-	unsigned long bank_addr;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		flash_info[i].size = 0;
-	}
-
-	tot_size = 0;
-
-	/* Detect Boot Flash */
-	bank_addr = CONFIG_SYS_FLASH0_BASE;
-	bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[0]);
-	if (bank_size > 0) {
-		(void)flash_protect(FLAG_PROTECT_CLEAR,
-			bank_addr,
-			bank_addr + bank_size - 1,
-			&flash_info[0]);
-	}
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Boot Flash Bank\n");
-	}
-	flash_info[0].size = bank_size;
-	tot_size += bank_size;
-
-	/* Detect Application Flash */
-	bank_addr = CONFIG_SYS_FLASH1_BASE;
-	for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[i]);
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			break;
-		}
-		if (bank_size > 0) {
-			(void)flash_protect(FLAG_PROTECT_CLEAR,
-				bank_addr,
-				bank_addr + bank_size - 1,
-				&flash_info[i]);
-		}
-		flash_info[i].size = bank_size;
-		tot_size += bank_size;
-		bank_addr += bank_size;
-	}
-	if (flash_info[1].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Application Flash Bank\n");
-	}
-
-	/* Protect monitor and environment sectors */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
-	flash_protect(FLAG_PROTECT_SET,
-		CONFIG_SYS_MONITOR_BASE,
-		CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
-		&flash_info[0]);
-#if 0xfffffffc >= CONFIG_SYS_FLASH0_BASE
-#if 0xfffffffc <= CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_FLASH0_SIZE - 1
-	flash_protect(FLAG_PROTECT_SET,
-		0xfffffffc, 0xffffffff,
-		&flash_info[0]);
-#endif
-#endif
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-	flash_protect(FLAG_PROTECT_SET,
-		CONFIG_ENV_ADDR,
-		CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
-		&flash_info[0]);
-#endif
-
-	return tot_size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_SST:	printf ("SST ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM040:	printf ("AM29F040 (512 Kbit, uniform sector size)\n");
-				break;
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AMDLV033C:	printf ("AM29LV033C (32 Mbit, uniform sector size)\n");
-				break;
-	case FLASH_AMDLV065D:	printf ("AM29LV065D (64 Mbit, uniform sector size)\n");
-				break;
-	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
-				break;
-	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
-				break;
-	case FLASH_SST040:	printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld KB in %d Sectors\n",
-		info->size >> 10, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	FLASH_WORD_SIZE value;
-	ulong base = (ulong)addr;
-	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
-	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
-	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
-
-	value = addr2[0];
-
-	switch (value) {
-	case (FLASH_WORD_SIZE)AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case (FLASH_WORD_SIZE)FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case (FLASH_WORD_SIZE)SST_MANUFACT:
-		info->flash_id = FLASH_MAN_SST;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr2[1];			/* device ID		*/
-
-	switch (value) {
-	case (FLASH_WORD_SIZE)AMD_ID_F040B:
-		info->flash_id += FLASH_AM040;
-		info->sector_count = 8;
-		info->size = 0x0080000; /* => 512 ko */
-		break;
-	case (FLASH_WORD_SIZE)AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;				/* => 0.5 MB		*/
-
-	case (FLASH_WORD_SIZE)AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;				/* => 0.5 MB		*/
-
-	case (FLASH_WORD_SIZE)AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (FLASH_WORD_SIZE)AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (FLASH_WORD_SIZE)AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (FLASH_WORD_SIZE)AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (FLASH_WORD_SIZE)AMD_ID_LV033C:
-		info->flash_id += FLASH_AMDLV033C;
-		info->sector_count = 64;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case (FLASH_WORD_SIZE)AMD_ID_LV065D:
-		info->flash_id += FLASH_AMDLV065D;
-		info->sector_count = 128;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-
-	case (FLASH_WORD_SIZE)AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case (FLASH_WORD_SIZE)AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case (FLASH_WORD_SIZE)SST_ID_xF800A:
-		info->flash_id += FLASH_SST800A;
-		info->sector_count = 16;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (FLASH_WORD_SIZE)SST_ID_xF160A:
-		info->flash_id += FLASH_SST160A;
-		info->sector_count = 32;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-	case (FLASH_WORD_SIZE)SST_ID_xF040:
-		info->flash_id += FLASH_SST040;
-		info->sector_count = 128;
-		info->size = 0x00080000;
-		break;				/* => 512KB		*/
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-
-	}
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-		(info->flash_id  == FLASH_AM040) ||
-		(info->flash_id == FLASH_AMDLV033C) ||
-		(info->flash_id == FLASH_AMDLV065D)) {
-		ulong sectsize = info->size / info->sector_count;
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * sectsize);
-	} else {
-	    if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-		}
-	    } else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	    }
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-
-		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
-		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
-			info->protect[i] = 0;
-		else
-			info->protect[i] = addr2[2] & 1;
-	}
-
-	/* switch to the read mode */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr2 = (FLASH_WORD_SIZE *)info->start[0];
-		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
-	volatile FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	start = get_timer (0);
-	last  = start;
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
-
-			/* Disable interrupts which might cause a timeout here */
-			flag = disable_interrupts();
-
-			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
-			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
-			addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
-			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
-			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
-			addr2[0] = (FLASH_WORD_SIZE)0x00300030;
-
-			/* re-enable interrupts if necessary */
-			if (flag)
-				enable_interrupts();
-
-			/* wait at least 80us - let's wait 1 ms */
-			udelay (1000);
-
-			while ((addr2[0] & 0x00800080) !=
-				(FLASH_WORD_SIZE) 0x00800080) {
-				if ((now=get_timer(start)) >
-					   CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					addr[0] = (FLASH_WORD_SIZE)0x00F000F0;
-					return 1;
-				}
-
-				/* show that we're waiting */
-				if ((now - last) > 1000) {  /* every second  */
-					putc ('.');
-					last = now;
-				}
-			}
-
-			addr[0] = (FLASH_WORD_SIZE)0x00F000F0;
-		}
-	}
-
-	printf (" done\n");
-
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
-	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
-	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
-	ulong start;
-	int flag;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((volatile ulong *)dest) & data) != data) {
-		printf("dest = %08lx, *dest = %08lx, data = %08lx\n",
-			dest, *(volatile ulong *)dest, data);
-		return 2;
-	}
-
-	for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) {
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
-		addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
-		addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
-		dest2[i] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer (0);
-		while ((dest2[i] & 0x00800080) != (data2[i] & 0x00800080)) {
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				addr2[0] = (FLASH_WORD_SIZE)0x00F000F0;
-				return (1);
-			}
-		}
-	}
-
-	addr2[0] = (FLASH_WORD_SIZE)0x00F000F0;
-
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S
deleted file mode 100644
index 721aaac3e74..00000000000
--- a/board/exbitgen/init.S
+++ /dev/null
@@ -1,1011 +0,0 @@
-/*----------------------------------------------------------------------+
- *       This source code is dual-licensed.  You may use it under the terms of
- *       the GNU General Public License version 2, or under the license below.
- *
- *       This source code has been made available to you by IBM on an AS-IS
- *       basis.  Anyone receiving this source is licensed under IBM
- *       copyrights to use it in any way he or she deems fit, including
- *       copying it, modifying it, compiling it, and redistributing it either
- *       with or without modifications.  No license under IBM patents or
- *       patent applications is to be implied by the copyright license.
- *
- *       Any user of this software should understand that IBM cannot provide
- *       technical support for this software and will not be responsible for
- *       any consequences resulting from the use of this software.
- *
- *       Any person who transfers this source code or any derivative work
- *       must include the IBM copyright notice, this paragraph, and the
- *       preceding two paragraphs in the transferred software.
- *
- *       COPYRIGHT   I B M   CORPORATION 1995
- *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
- *-----------------------------------------------------------------------
- */
-
-#include <config.h>
-#include <ppc4xx.h>
-#include "config.h"
-
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-#define FPGA_BRDC       0xF0300004
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#include "exbitgen.h"
-
-/* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */
-/* c-code declarations and consequently can't be included here). */
-/* (Possibly to be solved somehow else). */
-/*--------------------------------------------------------------------- */
-#define	   I2C_REGISTERS_BASE_ADDRESS 0xEF600500
-#define    IIC_MDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
-#define    IIC_SDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
-#define    IIC_LMADR	(I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
-#define    IIC_HMADR	(I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
-#define    IIC_CNTL	(I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
-#define    IIC_MDCNTL	(I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
-#define    IIC_STS	(I2C_REGISTERS_BASE_ADDRESS+IICSTS)
-#define    IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
-#define    IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
-#define    IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define    IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV)
-#define    IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
-#define    IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
-#define    IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
-#define    IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
-
-/* MDCNTL Register Bit definition */
-#define    IIC_MDCNTL_HSCL 0x01
-#define    IIC_MDCNTL_EUBS 0x02
-#define    IIC_MDCNTL_FMDB 0x40
-#define    IIC_MDCNTL_FSDB 0x80
-
-/* CNTL Register Bit definition */
-#define    IIC_CNTL_PT     0x01
-#define    IIC_CNTL_READ   0x02
-#define    IIC_CNTL_CHT    0x04
-
-/* STS Register Bit definition */
-#define    IIC_STS_PT	   0X01
-#define    IIC_STS_ERR	   0X04
-#define    IIC_STS_MDBS    0X20
-
-/* EXTSTS Register Bit definition */
-#define    IIC_EXTSTS_XFRA 0X01
-#define    IIC_EXTSTS_ICT  0X02
-#define    IIC_EXTSTS_LA   0X04
-
-/* LED codes used for inditing progress and errors during read of DIMM SPD.  */
-/*--------------------------------------------------------------------- */
-#define LED_SDRAM_CODE_1  0xef
-#define LED_SDRAM_CODE_2  0xee
-#define LED_SDRAM_CODE_3  0xed
-#define LED_SDRAM_CODE_4  0xec
-#define LED_SDRAM_CODE_5  0xeb
-#define LED_SDRAM_CODE_6  0xea
-#define LED_SDRAM_CODE_7  0xe9
-#define LED_SDRAM_CODE_8  0xe8
-#define LED_SDRAM_CODE_9  0xe7
-#define LED_SDRAM_CODE_10 0xe6
-#define LED_SDRAM_CODE_11 0xe5
-#define LED_SDRAM_CODE_12 0xe4
-#define LED_SDRAM_CODE_13 0xe3
-#define LED_SDRAM_CODE_14 0xe2
-#define LED_SDRAM_CODE_15 0xe1
-#define LED_SDRAM_CODE_16 0xe0
-
-
-#define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100
-
-#define FLASH_8bit_AP   0x9B015480
-#define FLASH_8bit_CR   0xFFF18000 /* 1MB(min), 8bit, R/W */
-
-#define FLASH_32bit_AP  0x9B015480
-#define FLASH_32bit_CR  0xFFE3C000 /* 2MB, 32bit, R/W */
-
-
-#define WDCR_EBC(reg,val) addi    r4,0,reg;\
-	mtdcr   EBC0_CFGADDR,r4;\
-	addis   r4,0,val@h;\
-	ori     r4,r4,val@l;\
-	mtdcr   EBC0_CFGDATA,r4
-
-/*---------------------------------------------------------------------
- * Function:     ext_bus_cntlr_init
- * Description:  Initializes the External Bus Controller for the external
- *		peripherals. IMPORTANT: For pass1 this code must run from
- *		cache since you can not reliably change a peripheral banks
- *		timing register (pbxap) while running code from that bank.
- *		For ex., since we are running from ROM on bank 0, we can NOT
- *		execute the code that modifies bank 0 timings from ROM, so
- *		we run it from cache.
- *	Bank 0 - Boot flash
- *	Bank 1-4 - application flash
- *	Bank 5 - CPLD
- *	Bank 6 - not used
- *	Bank 7 - Heathrow chip
- *---------------------------------------------------------------------
- */
-	.globl	ext_bus_cntlr_init
-ext_bus_cntlr_init:
-	mflr    r4                      /* save link register */
-	bl      ..getAddr
-..getAddr:
-	mflr    r3                      /* get address of ..getAddr */
-	mtlr    r4                      /* restore link register */
-	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
-	mtctr   r4                      /* 10 cache lines to fit this function */
-					/* in cache (gives us 8x10=80 instrctns) */
-..ebcloop:
-	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
-	addi    r3,r3,32		/* move to next cache line */
-	bdnz    ..ebcloop               /* continue for 10 cache lines */
-
-	mflr	r31			/* save link register */
-
-	/*-----------------------------------------------------------
-	 * Delay to ensure all accesses to ROM are complete before changing
-	 * bank 0 timings. 200usec should be enough.
-	 *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
-	 *-----------------------------------------------------------
-	 */
-
-	addis	r3,0,0x0
-	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
-	mtctr   r3
-..spinlp:
-	bdnz    ..spinlp                /* spin loop */
-
-	/*---------------------------------------------------------------
-	 * Memory Bank 0 (Boot Flash) initialization
-	 *---------------------------------------------------------------
-	 */
-	WDCR_EBC(PB1AP, FLASH_32bit_AP)
-	WDCR_EBC(PB0CR, 0xffe38000)
-/*pnc	WDCR_EBC(PB0CR, FLASH_32bit_CR) */
-
-	/*---------------------------------------------------------------
-	 * Memory Bank 5 (CPLD) initialization
-	 *---------------------------------------------------------------
-	 */
-	WDCR_EBC(PB5AP, 0x01010040)
-/*jsa recommendation:		WDCR_EBC(PB5AP, 0x00010040) */
-	WDCR_EBC(PB5CR, 0x10038000)
-
-	/*--------------------------------------------------------------- */
-	/* Memory Bank 6 (not used) initialization */
-	/*--------------------------------------------------------------- */
-	WDCR_EBC(PB6CR, 0x00000000)
-
-	/* Read HW ID to determine whether old H2 board or new generic CPU board */
-	addis	r3, 0,  HW_ID_ADDR@h
-	ori	r3, r3, HW_ID_ADDR@l
-	lbz     r3,0x0000(r3)
-	cmpi	0, r3, 1          /* if (HW_ID==1) */
-	beq	setup_h2evalboard /* then jump */
-	cmpi	0, r3, 2          /* if (HW_ID==2) */
-	beq	setup_genieboard  /* then jump */
-	cmpi	0, r3, 3          /* if (HW_ID==3) */
-	beq	setup_genieboard  /* then jump */
-
-setup_genieboard:
-	/*--------------------------------------------------------------- */
-	/* Memory Bank 1 (Application Flash) initialization for generic CPU board */
-	/*--------------------------------------------------------------- */
-/*	WDCR_EBC(PB1AP, 0x7b015480)	/###* T.B.M. */
-/*	WDCR_EBC(PB1AP, 0x7F8FFE80)	/###* T.B.M. */
-	WDCR_EBC(PB1AP, 0x9b015480)	/* hlb-20020207: burst 8 bit 6 cycles  */
-
-/*	WDCR_EBC(PB1CR, 0x20098000)	/###* 16 MB */
-	WDCR_EBC(PB1CR, 0x200B8000)	/* 32 MB */
-
-	/*--------------------------------------------------------------- */
-	/* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
-	/*--------------------------------------------------------------- */
-	WDCR_EBC(PB4AP, 0x01010000)	/*  */
-	WDCR_EBC(PB4CR, 0x1021c000)	/*  */
-
-	/*--------------------------------------------------------------- */
-	/* Memory Bank 7 (Heathrow chip on Reference board) initialization */
-	/*--------------------------------------------------------------- */
-	WDCR_EBC(PB7AP, 0x200ffe80)	/* No Ready, many wait states (let reflections die out) */
-	WDCR_EBC(PB7CR, 0X4001A000)
-
-	bl	setup_continue
-
-
-setup_h2evalboard:
-	/*--------------------------------------------------------------- */
-	/* Memory Bank 1 (Application Flash) initialization */
-	/*--------------------------------------------------------------- */
-	WDCR_EBC(PB1AP, 0x7b015480)	/* T.B.M. */
-/*3010	WDCR_EBC(PB1AP, 0x7F8FFE80)	/###* T.B.M. */
-	WDCR_EBC(PB1CR, 0x20058000)
-
-	/*--------------------------------------------------------------- */
-	/* Memory Bank 2 (Application Flash) initialization */
-	/*--------------------------------------------------------------- */
-	WDCR_EBC(PB2AP, 0x7b015480)	/* T.B.M. */
-/*3010	WDCR_EBC(PB2AP, 0x7F8FFE80)	/###* T.B.M. */
-	WDCR_EBC(PB2CR, 0x20458000)
-
-	/*--------------------------------------------------------------- */
-	/* Memory Bank 3 (Application Flash) initialization */
-	/*--------------------------------------------------------------- */
-	WDCR_EBC(PB3AP, 0x7b015480)	/* T.B.M. */
-/*3010	WDCR_EBC(PB3AP, 0x7F8FFE80)	/###* T.B.M. */
-	WDCR_EBC(PB3CR, 0x20858000)
-
-	/*--------------------------------------------------------------- */
-	/* Memory Bank 4 (Application Flash) initialization */
-	/*--------------------------------------------------------------- */
-	WDCR_EBC(PB4AP, 0x7b015480)	/* T.B.M. */
-/*3010	WDCR_EBC(PB4AP, 0x7F8FFE80)	/###* T.B.M. */
-	WDCR_EBC(PB4CR, 0x20C58000)
-
-	/*--------------------------------------------------------------- */
-	/* Memory Bank 7 (Heathrow chip) initialization */
-	/*--------------------------------------------------------------- */
-	WDCR_EBC(PB7AP, 0x02000280)	/* No Ready, 4 wait states */
-	WDCR_EBC(PB7CR, 0X4001A000)
-
-setup_continue:
-
-
-	mtlr    r31                     /* restore lr	 */
-	nop				/* pass2 DCR errata #8 */
-	blr
-
-/*--------------------------------------------------------------------- */
-/* Function:     sdram_init */
-/* Description:  Configures SDRAM memory banks. */
-/*--------------------------------------------------------------------- */
-	.globl  sdram_init
-
-sdram_init:
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
-	blr
-#else
-	mflr	r31
-
-	/* output SDRAM code  on LEDs */
-	addi	r4, 0, LED_SDRAM_CODE_1
-	addis	r5, 0, 0x1000
-	ori	r5, r5, 0x0001
-	stb	r4,0(r5)
-	eieio
-
-	/* Read contents of spd */
-	/*--------------------- */
-	bl	read_spd
-
-	/*----------------------------------------------------------- */
-	/* */
-	/* */
-	/* Update SDRAM timing register */
-	/* */
-	/* */
-	/*----------------------------------------------------------- */
-
-	/* Read  PLL feedback divider and calculate clock period of local bus in */
-	/* granularity of 10 ps. Save clock period in r30 */
-	/*-------------------------------------------------------------- */
-	mfdcr	r4, CPC0_PLLMR
-	addi	r9, 0, 25
-	srw	r4, r4, r9
-	andi.	r4, r4, 0x07
-	addis	r5, 0,  TIMEBASE_10PS@h
-	ori	r5, r5, TIMEBASE_10PS@l
-	divwu	r30, r5, r4
-
-	/* Determine CASL */
-	/*--------------- */
-	bl	find_casl	/* Returns CASL in r3 */
-
-	/* Calc trp_clocks = (trp * 100 + (clk - 1)) / clk */
-	/* (trp read from byte 27 in granularity of 1 ns) */
-	/*------------------------------------------------ */
-	mulli	r16, r16, 100
-	add	r16, r16, r30
-	addi	r6, 0, 1
-	subf	r16, r6, r16
-	divwu	r16, r16, r30
-
-	/* Calc trcd_clocks = (trcd * 100 + (clk - 1) ) / clk */
-	/* (trcd read from byte 29 in granularity of 1 ns) */
-	/*--------------------------------------------------- */
-	mulli	r17, r17, 100
-	add	r17, r17, r30
-	addi	r6, 0, 1
-	subf	r17, r6, r17
-	divwu	r17, r17, r30
-
-	/* Calc tras_clocks = (tras * 100 + (clk - 1) ) / clk */
-	/* (tras read from byte 30 in granularity of 1 ns) */
-	/*--------------------------------------------------- */
-	mulli	r18, r18, 100
-	add	r18, r18, r30
-	addi	r6, 0, 1
-	subf	r18, r6, r18
-	divwu	r18, r18, r30
-
-	/* Calc trc_clocks = trp_clocks + tras_clocks */
-	/*------------------------------------------- */
-	add	r18, r18, r16
-
-	/* CASL value */
-	/*----------- */
-	addi	r9, 0, 23
-	slw	r4, r3, r9
-
-	/* PTA = trp_clocks - 1 */
-	/*--------------------- */
-	addi	r6, 0, 1
-	subf	r5, r6, r16
-	addi	r9, 0, 18
-	slw	r5, r5, r9
-	or	r4, r4, r5
-
-	/* CTP = trc_clocks - trp_clocks - trcd_clocks - 1 */
-	/*------------------------------------------------ */
-	addi	r5, r18, 0
-	subf	r5, r16, r5
-	subf	r5, r17, r5
-	addi	r6, 0, 1
-	subf	r5, r6, r5
-	addi	r9, 0, 16
-	slw	r5, r5, r9
-	or	r4, r4, r5
-
-	/* LDF = 1 */
-	/*-------- */
-	ori	r4, r4, 0x4000
-
-	/* RFTA = trc_clocks - 4 */
-	/*---------------------- */
-	addi	r6, 0, 4
-	subf	r5, r6, r18
-	addi	r9, 0, 2
-	slw	r5, r5, r9
-	or	r4, r4, r5
-
-	/* RCD = trcd_clocks - 1 */
-	/*---------------------- */
-	addi	r6, 0, 1
-	subf	r5, r6, r17
-	or	r4, r4, r5
-
-	/*----------------------------------------------------------- */
-	/* Set SDTR1  */
-	/*----------------------------------------------------------- */
-	addi    r5,0,SDRAM0_TR
-	mtdcr   SDRAM0_CFGADDR,r5
-	mtdcr   SDRAM0_CFGDATA,r4
-
-	/*----------------------------------------------------------- */
-	/* */
-	/* */
-	/* Update memory bank 0-3 configuration registers */
-	/* */
-	/* */
-	/*----------------------------------------------------------- */
-
-	/* Build contents of configuration register for bank 0 into r6 */
-	/*------------------------------------------------------------ */
-	bl	find_mode	/* returns addressing mode in r3 */
-	addi	r29, r3, 0	/* save mode temporarily in r29 */
-	bl	find_size_code	/* returns size code in r3 */
-	addi	r9, 0, 17	/* bit offset of size code in configuration register */
-	slw	r3, r3, r9	/* */
-	addi	r9, 0, 13	/* bit offset of addressing mode in configuration register  */
-	slw	r29, r29, r9	/*  */
-	or	r3, r29, r3	/* merge size code and addressing mode */
-	ori	r6, r3, CONFIG_SYS_SDRAM_BASE + 1 /* insert base address and enable bank */
-
-	/* Calculate banksize r15 = (density << 22) / 2 */
-	/*--------------------------------------------- */
-	addi	r9, 0, 21
-	slw	r15, r15, r9
-
-	/* Set SDRAM bank 0 register and adjust r6 for next bank */
-	/*------------------------------------------------------ */
-	addi    r7,0,SDRAM0_B0CR
-	mtdcr   SDRAM0_CFGADDR,r7
-	mtdcr   SDRAM0_CFGDATA,r6
-
-	add	r6, r6, r15	/* add bank size to base address for next bank */
-
-	/* If two rows/banks then set SDRAM bank 1 register and adjust r6 for next bank */
-	/*---------------------------------------------------------------------------- */
-	cmpi	0, r12, 2
-	bne	b1skip
-
-	addi    r7,0,SDRAM0_B1CR
-	mtdcr   SDRAM0_CFGADDR,r7
-	mtdcr   SDRAM0_CFGDATA,r6
-
-	add	r6, r6, r15	/* add bank size to base address for next bank */
-
-	/* Set SDRAM bank 2 register and adjust r6 for next bank */
-	/*------------------------------------------------------ */
-b1skip:	addi    r7,0,SDRAM0_B2CR
-	mtdcr   SDRAM0_CFGADDR,r7
-	mtdcr   SDRAM0_CFGDATA,r6
-
-	add	r6, r6, r15	/* add bank size to base address for next bank */
-
-	/* If two rows/banks then set SDRAM bank 3 register */
-	/*------------------------------------------------ */
-	cmpi	0, r12, 2
-	bne	b3skip
-
-	addi    r7,0,SDRAM0_B3CR
-	mtdcr   SDRAM0_CFGADDR,r7
-	mtdcr   SDRAM0_CFGDATA,r6
-b3skip:
-
-	/*----------------------------------------------------------- */
-	/* Set RTR */
-	/*----------------------------------------------------------- */
-	cmpi	0, r30, 1600
-	bge	rtr_1
-	addis   r7, 0, 0x05F0	/* RTR value for 100Mhz */
-	bl	rtr_2
-rtr_1:	addis	r7, 0, 0x03F8
-rtr_2:	addi    r4,0,SDRAM0_RTR
-	mtdcr   SDRAM0_CFGADDR,r4
-	mtdcr   SDRAM0_CFGDATA,r7
-
-	/*----------------------------------------------------------- */
-	/* Delay to ensure 200usec have elapsed since reset. Assume worst */
-	/* case that the core is running 200Mhz: */
-	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
-	/*----------------------------------------------------------- */
-	addis   r3,0,0x0000
-	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
-	mtctr   r3
-..spinlp2:
-	bdnz    ..spinlp2               /* spin loop */
-
-	/*----------------------------------------------------------- */
-	/* Set memory controller options reg, MCOPT1. */
-	/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst  */
-	/* read/prefetch. */
-	/*----------------------------------------------------------- */
-	addi    r4,0,SDRAM0_CFG
-	mtdcr   SDRAM0_CFGADDR,r4
-	addis   r4,0,0x80C0             /* set DC_EN=1 */
-	ori     r4,r4,0x0000
-	mtdcr   SDRAM0_CFGDATA,r4
-
-
-	/*----------------------------------------------------------- */
-	/* Delay to ensure 10msec have elapsed since reset. This is */
-	/* required for the MPC952 to stabalize. Assume worst */
-	/* case that the core is running 200Mhz: */
-	/*   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
-	/* This delay should occur before accessing SDRAM. */
-	/*----------------------------------------------------------- */
-	addis   r3,0,0x001E
-	ori     r3,r3,0x8480          /* ensure 10msec have passed since reset */
-	mtctr   r3
-..spinlp3:
-	bdnz    ..spinlp3                /* spin loop */
-
-	/* output SDRAM code  on LEDs */
-	addi	r4, 0, LED_SDRAM_CODE_16
-	addis	r5, 0, 0x1000
-	ori	r5, r5, 0x0001
-	stb	r4,0(r5)
-	eieio
-
-	mtlr    r31                     /* restore lr */
-	blr
-
-/*--------------------------------------------------------------------- */
-/* Function:    read_spd */
-/* Description: Reads contents of SPD and saves parameters to be used for */
-/*		configuration in dedicated registers (see code below). */
-/*---------------------------------------------------------------------	 */
-
-#define WRITE_I2C(reg,val) \
-	addi    r3,0,val;\
-	addis   r4, 0, 0xef60;\
-	ori     r4, r4, 0x0500 + reg;\
-	stb     r3, 0(r4);\
-	eieio
-
-#define READ_I2C(reg) \
-	addis   r3, 0, 0xef60;\
-	ori     r3, r3, 0x0500 + reg;\
-	lbz     r3, 0x0000(r3);\
-	eieio
-
-read_spd:
-
-	mflr	r5
-
-	/* Initialize i2c */
-	/*--------------- */
-	WRITE_I2C(IICLMADR, 0x00)	/* clear lo master address */
-	WRITE_I2C(IICHMADR, 0x00)	/* clear hi master address */
-	WRITE_I2C(IICLSADR, 0x00)	/* clear lo slave address */
-	WRITE_I2C(IICHSADR, 0x00)	/* clear hi slave address */
-	WRITE_I2C(IICSTS, 0x08)		/* update status register */
-	WRITE_I2C(IICEXTSTS, 0x8f)
-	WRITE_I2C(IIC0_CLKDIV, 0x05)
-	WRITE_I2C(IICINTRMSK, 0x00)	/* no interrupts */
-	WRITE_I2C(IICXFRCNT, 0x00)	/* clear transfer count */
-	WRITE_I2C(IICXTCNTLSS, 0xf0)	/* clear extended control & stat */
-	WRITE_I2C(IICMDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB)	/* mode control */
-	READ_I2C(IICMDCNTL)
-	ori	r3, r3, IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL
-	WRITE_I2C(IICMDCNTL, r3)	/* mode control */
-	WRITE_I2C(IICCNTL, 0x00)	/* clear control reg */
-
-	/* Wait until initialization completed */
-	/*------------------------------------ */
-	bl	wait_i2c_transfer_done
-
-	WRITE_I2C(IICHMADR, 0x00)	/* 7-bit addressing */
-	WRITE_I2C(IICLMADR, SDRAM_SPD_WRITE_ADDRESS)
-
-	/* Write 0 into buffer(start address) */
-	/*----------------------------------- */
-	WRITE_I2C(IICMDBUF, 0x00);
-
-	/* Wait a little */
-	/*-------------- */
-	addis   r3,0,0x0000
-	ori     r3,r3,0xA000
-	mtctr   r3
-in02:	bdnz    in02
-
-	/* Issue write command */
-	/*-------------------- */
-	WRITE_I2C(IICCNTL, IIC_CNTL_PT)
-	bl	wait_i2c_transfer_done
-
-	/* Read 128 bytes */
-	/*--------------- */
-	addi	r7, 0, 0	/* byte counter in r7 */
-	addi	r8, 0, 0	/* checksum in r8 */
-rdlp:
-	/* issue read command */
-	/*------------------- */
-	cmpi	0, r7, 127
-	blt	rd01
-	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT)
-	bl	rd02
-rd01:	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT)
-rd02:	bl	wait_i2c_transfer_done
-
-	/* Fetch byte from buffer */
-	/*----------------------- */
-	READ_I2C(IICMDBUF)
-
-	/* Retrieve parameters that are going to be used during configuration. */
-	/* Save them in dedicated registers. */
-	/*------------------------------------------------------------ */
-	cmpi	0, r7, 3	/* Save byte 3 in r10 */
-	bne	rd10
-	addi	r10, r3, 0
-rd10:	cmpi	0, r7, 4	/* Save byte 4 in r11 */
-	bne	rd11
-	addi	r11, r3, 0
-rd11:	cmpi	0, r7, 5	/* Save byte 5 in r12 */
-	bne	rd12
-	addi	r12, r3, 0
-rd12:	cmpi	0, r7, 17	/* Save byte 17 in r13 */
-	bne	rd13
-	addi	r13, r3, 0
-rd13:	cmpi	0, r7, 18	/* Save byte 18 in r14 */
-	bne	rd14
-	addi	r14, r3, 0
-rd14:	cmpi	0, r7, 31	/* Save byte 31 in r15 */
-	bne	rd15
-	addi	r15, r3, 0
-rd15:	cmpi	0, r7, 27	/* Save byte 27 in r16 */
-	bne	rd16
-	addi	r16, r3, 0
-rd16:	cmpi	0, r7, 29	/* Save byte 29 in r17 */
-	bne	rd17
-	addi	r17, r3, 0
-rd17:	cmpi	0, r7, 30	/* Save byte 30 in r18 */
-	bne	rd18
-	addi	r18, r3, 0
-rd18:	cmpi	0, r7, 9	/* Save byte 9 in r19 */
-	bne	rd19
-	addi	r19, r3, 0
-rd19:	cmpi	0, r7, 23	/* Save byte 23 in r20 */
-	bne	rd20
-	addi	r20, r3, 0
-rd20:	cmpi	0, r7, 25	/* Save byte 25 in r21 */
-	bne	rd21
-	addi	r21, r3, 0
-rd21:
-
-	/* Calculate checksum of the first 63 bytes */
-	/*----------------------------------------- */
-	cmpi	0, r7, 63
-	bgt	rd31
-	beq	rd30
-	add	r8, r8, r3
-	bl	rd31
-
-	/* Verify checksum at byte 63 */
-	/*--------------------------- */
-rd30:	andi.	r8, r8, 0xff		/* use only 8 bits */
-	cmp	0, r8, r3
-	beq	rd31
-	addi	r4, 0, LED_SDRAM_CODE_8
-	addis	r5, 0, 0x1000
-	ori	r5, r5, 0x0001
-	stb	r4,0(r5)
-	eieio
-rderr:	bl	rderr
-
-rd31:
-
-	/* Increment byte counter and check whether all bytes have been read. */
-	/*------------------------------------------------------------------- */
-	addi	r7, r7, 1
-	cmpi	0, r7, 127
-	bgt	rd05
-	bl	rdlp
-rd05:
-	mtlr    r5                     /* restore lr */
-	blr
-
-wait_i2c_transfer_done:
-	mflr	r6
-wt01:	READ_I2C(IICSTS)
-	andi.	r4, r3, IIC_STS_PT
-	cmpi	0, r4, IIC_STS_PT
-	beq	wt01
-	mtlr    r6                     /* restore lr */
-	blr
-
-/*--------------------------------------------------------------------- */
-/* Function:    find_mode */
-/* Description: Determines addressing mode to be used dependent on   */
-/*		number of rows (r10 = byte 3 from SPD), number of columns (r11 = */
-/*		byte 4 from SPD) and number of banks (r13 = byte 17 from SPD). */
-/*		mode is returned in r3. */
-/* (It would be nicer having a table, pnc). */
-/*---------------------------------------------------------------------	 */
-find_mode:
-
-	mflr	r5
-
-	cmpi	0, r10, 11
-	bne	fm01
-	cmpi	0, r11, 9
-	bne	fm01
-	cmpi	0, r13, 2
-	bne	fm01
-	addi	r3, 0, 1
-	bl	fmfound
-
-fm01:	cmpi	0, r10, 11
-	bne	fm02
-	cmpi	0, r11, 10
-	bne	fm02
-	cmpi	0, r13, 2
-	bne	fm02
-	addi	r3, 0, 1
-	bl	fmfound
-
-fm02:	cmpi	0, r10, 12
-	bne	fm03
-	cmpi	0, r11, 9
-	bne	fm03
-	cmpi	0, r13, 4
-	bne	fm03
-	addi	r3, 0, 2
-	bl	fmfound
-
-fm03:	cmpi	0, r10, 12
-	bne	fm04
-	cmpi	0, r11, 10
-	bne	fm04
-	cmpi	0, r13, 4
-	bne	fm04
-	addi	r3, 0, 2
-	bl	fmfound
-
-fm04:	cmpi	0, r10, 13
-	bne	fm05
-	cmpi	0, r11, 9
-	bne	fm05
-	cmpi	0, r13, 4
-	bne	fm05
-	addi	r3, 0, 3
-	bl	fmfound
-
-fm05:	cmpi	0, r10, 13
-	bne	fm06
-	cmpi	0, r11, 10
-	bne	fm06
-	cmpi	0, r13, 4
-	bne	fm06
-	addi	r3, 0, 3
-	bl	fmfound
-
-fm06:	cmpi	0, r10, 13
-	bne	fm07
-	cmpi	0, r11, 11
-	bne	fm07
-	cmpi	0, r13, 4
-	bne	fm07
-	addi	r3, 0, 3
-	bl	fmfound
-
-fm07:	cmpi	0, r10, 12
-	bne	fm08
-	cmpi	0, r11, 8
-	bne	fm08
-	cmpi	0, r13, 2
-	bne	fm08
-	addi	r3, 0, 4
-	bl	fmfound
-
-fm08:	cmpi	0, r10, 12
-	bne	fm09
-	cmpi	0, r11, 8
-	bne	fm09
-	cmpi	0, r13, 4
-	bne	fm09
-	addi	r3, 0, 4
-	bl	fmfound
-
-fm09:	cmpi	0, r10, 11
-	bne	fm10
-	cmpi	0, r11, 8
-	bne	fm10
-	cmpi	0, r13, 2
-	bne	fm10
-	addi	r3, 0, 5
-	bl	fmfound
-
-fm10:	cmpi	0, r10, 11
-	bne	fm11
-	cmpi	0, r11, 8
-	bne	fm11
-	cmpi	0, r13, 4
-	bne	fm11
-	addi	r3, 0, 5
-	bl	fmfound
-
-fm11:	cmpi	0, r10, 13
-	bne	fm12
-	cmpi	0, r11, 8
-	bne	fm12
-	cmpi	0, r13, 2
-	bne	fm12
-	addi	r3, 0, 6
-	bl	fmfound
-
-fm12:	cmpi	0, r10, 13
-	bne	fm13
-	cmpi	0, r11, 8
-	bne	fm13
-	cmpi	0, r13, 4
-	bne	fm13
-	addi	r3, 0, 6
-	bl	fmfound
-
-fm13:	cmpi	0, r10, 13
-	bne	fm14
-	cmpi	0, r11, 9
-	bne	fm14
-	cmpi	0, r13, 2
-	bne	fm14
-	addi	r3, 0, 7
-	bl	fmfound
-
-fm14:	cmpi	0, r10, 13
-	bne	fm15
-	cmpi	0, r11, 10
-	bne	fm15
-	cmpi	0, r13, 2
-	bne	fm15
-	addi	r3, 0, 7
-	bl	fmfound
-
-fm15:
-	/* not found, error code to be issued on LEDs */
-	addi	r7, 0, LED_SDRAM_CODE_2
-	addis	r6, 0, 0x1000
-	ori	r6, r6, 0x0001
-	stb	r7,0(r6)
-	eieio
-fmerr:	bl	fmerr
-
-fmfound:addi	r6, 0, 1
-	subf	r3, r6, r3
-
-	mtlr    r5                     /* restore lr */
-	blr
-
-/*--------------------------------------------------------------------- */
-/* Function:    find_size_code */
-/* Description: Determines size code to be used in configuring SDRAM controller */
-/*		dependent on density (r15 = byte 31 from SPD) */
-/*--------------------------------------------------------------------- */
-find_size_code:
-
-	mflr	r5
-
-	addi	r3, r15, 0	/* density */
-	addi	r7, 0, 0
-fs01:	andi.	r6, r3, 0x01
-	cmpi	0, r6, 1
-	beq	fs04
-
-	addi	r7, r7, 1
-	cmpi	0, r7, 7
-	bge	fs02
-	addi	r9, 0, 1
-	srw	r3, r3, r9
-	bl	fs01
-
-	/* not found, error code to be issued on LEDs */
-fs02:	addi	r4, 0, LED_SDRAM_CODE_3
-	addis	r8, 0, 0x1000
-	ori	r8, r8, 0x0001
-	stb	r4,0(r8)
-	eieio
-fs03:	bl	fs03
-
-fs04:	addi	r3, r7, 0
-	cmpi	0, r3, 0
-	beq	fs05
-	addi	r6, 0, 1
-	subf	r3, r6, r3
-fs05:
-	mtlr    r5                     /* restore lr */
-	blr
-
-/*--------------------------------------------------------------------- */
-/* Function:    find_casl */
-/* Description: Determines CAS latency */
-/*--------------------------------------------------------------------- */
-find_casl:
-
-	mflr	r5
-
-	andi.	r14, r14, 0x7f	/* r14 holds supported CAS latencies */
-	addi	r3, 0, 0xff	/* preset determined CASL */
-	addi	r4, 0, 6	/* Start at bit 6 of supported CAS latencies */
-	addi	r2, 0, 0	/* Start finding highest CAS latency */
-
-fc01:	srw	r6, r14, r4	/*  */
-	andi.	r6, r6, 0x01	/*  */
-	cmpi	0, r6, 1	/* Check bit for current latency */
-	bne	fc06		/* If not supported, go to next */
-
-	cmpi	0, r2, 2	/* Check if third-highest latency */
-	bge	fc04		/* If so, go calculate with another format */
-
-	cmpi	0, r2, 0	/* Check if highest latency */
-	bgt	fc02		/* */
-	addi	r7, r19, 0	/* SDRAM cycle time for highest CAS latenty */
-
-	bl	fc03
-fc02:
-	addi	r7, r20, 0	/* SDRAM cycle time for next-highest CAS latenty */
-fc03:
-	addi	r8, r7, 0
-	addi	r9, 0, 4
-	srw	r7, r7, r9
-	andi.	r7, r7, 0x0f
-	mulli	r7, r7, 100
-	andi.	r8, r8, 0x0f
-	mulli	r8, r8, 10
-	add	r7, r7, r8
-	cmp	0, r7, r30
-	bgt	fc05
-	addi	r3, r2, 0
-	bl	fc05
-fc04:
-	addi	r7, r21, 0	/* SDRAM cycle time for third-highest CAS latenty */
-	addi	r8, r7, 0
-	addi	r9, 0, 2
-	srw	r7, r7, r9
-	andi.	r7, r7, 0x3f
-	mulli	r7, r7, 100
-	andi.	r8, r8, 0x03
-	mulli	r8, r8, 25
-	add	r7, r7, r8
-
-	cmp	0, r7, r30
-	bgt	fc05
-	addi	r3, r2, 0
-
-fc05:	addi	r2, r2, 1	/* next latency */
-	cmpi	0, r2, 3
-	bge	fc07
-fc06:	addi	r6, 0, 1
-	subf	r4, r6, r4
-	cmpi	0, r4, 0
-	bne	fc01
-
-fc07:
-
-	mtlr    r5		/* restore lr */
-	blr
-#endif
-
-
-/*  Peripheral Bank 1 Access Parameters */
-/*     0	BME = 1	; burstmode enabled */
-/*    " 1:8"	TWT=00110110	;Transfer wait (details below) */
-/*     1:5	FWT=00110	; first wait = 6 cycles */
-/*     6:8	BWT=110	; burst wait = 6 cycles */
-/*     9:11	000	; reserved */
-/*     12:13	CSN=00	; chip select on timing = 0 */
-/*     14:15	OEN=01	; output enable  */
-/*     16:17	WBN=01	; write byte enable on timing 1 cycle */
-/*     18:19	WBF=01	; write byte enable off timing 1 cycle */
-/*     20:22	TH=010	; transfer hold = 2 cycles */
-/*     23	RE=0	; ready enable = disabled */
-/*     24	SOR=1	; sample on ready = same PerClk */
-/*     25	BEM=0	; byte enable mode = only for write cycles */
-/*     26	PEN=0	; parity enable = disable */
-/*     27:31	00000	;reserved */
-/* */
-/* 1 + 00110 + 110 + 000 + 00 + 01 + 01 + 01 + 010 + 0 + 1 + 0 + 0 + 00000 = 0x9b015480 */
-/* */
-/* */
-/*	Code for BDI probe: */
-/* */
-/* WDCR    18      0x00000011      ;Select PB1AP */
-/* WDCR    19      0x1b015480      ;PB1AP: Flash */
-/* */
-/* Peripheral Bank 0 Access Parameters */
-/* 0:11	BAS=0x200	; base address select = 0x200 * 0x100000 (1MB) =  */
-/* 12:14	BS=100	; bank size =  16MB (100) / 32MB (101) */
-/* 15:16	BU=11	; bank usage = read/write */
-/* 17:18	BW=00	; bus width = 8-bit */
-/* 19:31		; reserved */
-/* */
-/* 0x200 + 100 + 11 + 00 + 0 0000 0000 0000 = 0x20098000 */
-/* WDCR    18      0x00000001      ;Select PB1CR */
-/* WDCR    19      0x20098000      ;PB1CR: 1MB at 0x00100000, r/w, 8bit */
-
-/* For CPLD */
-/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */
-/*	WDCR_EBC(PB5AP, 0x01010040) */
-/*jsa recommendation:		WDCR_EBC(PB5AP, 0x00010040) */
-/*	WDCR_EBC(PB5CR, 0X10018000) */
-/* Access parms */
-/*   100   3      8          0    0    0 */
-/* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */
-/* Address :	0x10000000 */
-/* Size:	2 MB */
-/* Usage:	read/write */
-/* Width:	32 bit */
-
-/* For Genie onboard fpga 32 bit interface */
-/* 0      1      0         1         0         0         0            0 */
-/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 0 + 0 + 00000 */
-/* 0x01010000 */
-/* Access parms */
-/*   102   1      c          0    0    0 */
-/* 0x102 + 000 + 11 + 10 + 0 0000 0000 0000 = 0x1021c000 */
-/* Address :	0x10200000 */
-/* Size:	2 MB */
-/* Usage:	read/write */
-/* Width:	32 bit */
-
-/* Walnut fpga PB7AP */
-/* 0      1      8         1         5         2         8            0 */
-/* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */
-/* Walnut fpga PB7CR */
-/* 0xF0318000 */
-/*  */
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index d4ba043b283..4f557329f48 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -159,7 +159,8 @@ int board_eth_init(bd_t *bd)
 		int i;
 
 		for (i = 0; i < ARRAY_SIZE(uec_info); i++)
-			uec_info[i].enet_interface = ENET_1000_RGMII_RXID;
+			uec_info[i].enet_interface_type = RGMII_RXID;
+			uec_info[i].speed = 1000;
 	}
 	return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
 }
diff --git a/board/freescale/mpc8569mds/config.mk b/board/freescale/mpc8569mds/config.mk
index 962f79b7477..7de0f7cf7d6 100644
--- a/board/freescale/mpc8569mds/config.mk
+++ b/board/freescale/mpc8569mds/config.mk
@@ -23,4 +23,13 @@
 #
 # mpc8569mds board
 #
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+endif
+endif
+
+ifndef TEXT_BASE
 TEXT_BASE = 0xfff80000
+endif
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
index 3b8ee050da1..73dcc3e66c5 100644
--- a/board/freescale/mpc8569mds/tlb.c
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -90,6 +90,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_64M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_256K, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+			CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile
new file mode 100644
index 00000000000..eb12fc51fd9
--- /dev/null
+++ b/board/freescale/mx51evk/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx51evk.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/exbitgen/config.mk b/board/freescale/mx51evk/config.mk
index 42ea0c6d78f..c8279ec8cbd 100644
--- a/board/exbitgen/config.mk
+++ b/board/freescale/mx51evk/config.mk
@@ -1,6 +1,5 @@
 #
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -21,13 +20,6 @@
 # MA 02111-1307 USA
 #
 
-#
-# ExbitGen board
-#
-
-LDFLAGS += $(LINKER_UNDEFS)
-
-TEXT_BASE := 0xFFF80000
-#TEXT_BASE := 0x00100000
-
-PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
+LDSCRIPT = cpu/$(CPU)/$(SOC)/u-boot.lds
+TEXT_BASE = 0x97800000
+IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg
new file mode 100644
index 00000000000..db09913f49e
--- /dev/null
+++ b/board/freescale/mx51evk/imximage.cfg
@@ -0,0 +1,119 @@
+#
+# (C Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# Boot Device : one of
+# spi_flash, nand, onenand, sd_card
+
+BOOT_FROM	spi
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type           Address        Value
+#
+# where:
+#	Addr-type register length (1,2 or 4 bytes)
+#	Address	  absolute address of the register
+#	value	  value to be stored in the register
+
+# Setting IOMUXC
+DATA 4 0x73FA88a0 0x200
+DATA 4 0x73FA850c 0x20c5
+DATA 4 0x73FA8510 0x20c5
+DATA 4 0x73FA883c 0x2
+DATA 4 0x73FA8848 0x2
+DATA 4 0x73FA84b8 0xe7
+DATA 4 0x73FA84bc 0x45
+DATA 4 0x73FA84c0 0x45
+DATA 4 0x73FA84c4 0x45
+DATA 4 0x73FA84c8 0x45
+DATA 4 0x73FA8820 0x0
+DATA 4 0x73FA84a4 0x3
+DATA 4 0x73FA84a8 0x3
+DATA 4 0x73FA84ac 0xe3
+DATA 4 0x73FA84b0 0xe3
+DATA 4 0x73FA84b4 0xe3
+DATA 4 0x73FA84cc 0xe3
+DATA 4 0x73FA84d0 0xe2
+
+DATA 4 0x73FA882c 0x6
+DATA 4 0x73FA88a4 0x6
+DATA 4 0x73FA88ac 0x6
+DATA 4 0x73FA88b8 0x6
+
+# Setting DDR for micron
+# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+# CAS=3 BL=4
+# ESDCTL_ESDCTL0
+DATA 4 0x83FD9000 0x82a20000
+# ESDCTL_ESDCTL1
+DATA 4 0x83FD9008 0x82a20000
+# ESDCTL_ESDMISC
+DATA 4 0x83FD9010 0x000ad0d0
+# ESDCTL_ESDCFG0
+DATA 4 0x83FD9004 0x333574aa
+# ESDCTL_ESDCFG1
+DATA 4 0x83FD900C 0x333574aa
+
+# Init DRAM on CS0
+# ESDCTL_ESDSCR
+DATA 4 0x83FD9014 0x04008008
+DATA 4 0x83FD9014 0x0000801a
+DATA 4 0x83FD9014 0x0000801b
+DATA 4 0x83FD9014 0x00448019
+DATA 4 0x83FD9014 0x07328018
+DATA 4 0x83FD9014 0x04008008
+DATA 4 0x83FD9014 0x00008010
+DATA 4 0x83FD9014 0x00008010
+DATA 4 0x83FD9014 0x06328018
+DATA 4 0x83FD9014 0x03808019
+DATA 4 0x83FD9014 0x00408019
+DATA 4 0x83FD9014 0x00008000
+
+# Init DRAM on CS1
+DATA 4 0x83FD9014 0x0400800c
+DATA 4 0x83FD9014 0x0000801e
+DATA 4 0x83FD9014 0x0000801f
+DATA 4 0x83FD9014 0x0000801d
+DATA 4 0x83FD9014 0x0732801c
+DATA 4 0x83FD9014 0x0400800c
+DATA 4 0x83FD9014 0x00008014
+DATA 4 0x83FD9014 0x00008014
+DATA 4 0x83FD9014 0x0632801c
+DATA 4 0x83FD9014 0x0380801d
+DATA 4 0x83FD9014 0x0040801d
+DATA 4 0x83FD9014 0x00008004
+
+# Write to CTL0
+DATA 4 0x83FD9000 0xb2a20000
+# Write to CTL1
+DATA 4 0x83FD9008 0xb2a20000
+# ESDMISC
+DATA 4 0x83FD9010 0x000ad6d0
+#ESDCTL_ESDCDLYGD
+DATA 4 0x83FD9034 0x90000000
+DATA 4 0x83FD9014 0x00000000
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
new file mode 100644
index 00000000000..af1b0bd8bc7
--- /dev/null
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -0,0 +1,397 @@
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx51_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include "mx51evk.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+struct io_board_ctrl *mx51_io_board;
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR, 1, 1},
+	{MMC_SDHC2_BASE_ADDR, 1, 1},
+};
+#endif
+
+u32 get_board_rev(void)
+{
+	return system_rev;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+			PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+			PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
+
+	mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
+	mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
+	mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
+	mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
+}
+
+static void setup_expio(void)
+{
+	u32 reg;
+	struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
+	struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR;
+
+	/* CS5 setup */
+	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
+	writel(0x00410089, &pweim[5].csgcr1);
+	writel(0x00000002, &pweim[5].csgcr2);
+
+	/* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
+	writel(0x32260000, &pweim[5].csrcr1);
+
+	/* APR = 0 */
+	writel(0x00000000, &pweim[5].csrcr2);
+
+	/*
+	 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
+	 * WCSA=0, WCSN=0
+	 */
+	writel(0x72080F00, &pweim[5].cswcr1);
+
+	mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR +
+						IO_BOARD_OFFSET);
+	if ((readw(&mx51_io_board->id1) == 0xAAAA) &&
+		(readw(&mx51_io_board->id2) == 0x5555)) {
+		if (is_soc_rev(CHIP_REV_2_0) < 0) {
+			reg = readl(&pclkctl->cbcdr);
+			reg = (reg & (~0x70000)) | 0x30000;
+			writel(reg, &pclkctl->cbcdr);
+			/* make sure divider effective */
+			while (readl(&pclkctl->cdhipr) != 0)
+				;
+			writel(0x0, &pclkctl->ccdr);
+		}
+	} else {
+		/* CS1 */
+		writel(0x00410089, &pweim[1].csgcr1);
+		writel(0x00000002, &pweim[1].csgcr2);
+		/*  RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
+		writel(0x32260000, &pweim[1].csrcr1);
+		/* APR=0 */
+		writel(0x00000000, &pweim[1].csrcr2);
+		/*
+		 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
+		 * WEN=0, WCSA=0, WCSN=0
+		 */
+		writel(0x72080F00, &pweim[1].cswcr1);
+		mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR +
+						IO_BOARD_OFFSET);
+	}
+
+	/* Reset interrupt status reg */
+	writew(0x1F, &(mx51_io_board->int_rest));
+	writew(0x00, &(mx51_io_board->int_rest));
+	writew(0xFFFF, &(mx51_io_board->int_mask));
+
+	/* Reset the XUART and Ethernet controllers */
+	reg = readw(&(mx51_io_board->sw_reset));
+	reg |= 0x9;
+	writew(reg, &(mx51_io_board->sw_reset));
+	reg &= ~0x9;
+	writew(reg, &(mx51_io_board->sw_reset));
+}
+
+static void setup_iomux_fec(void)
+{
+	/*FEC_MDIO*/
+	mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
+
+	/*FEC_MDC*/
+	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
+
+	/* FEC RDATA[3] */
+	mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
+
+	/* FEC RDATA[2] */
+	mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
+
+	/* FEC RDATA[1] */
+	mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
+
+	/* FEC RDATA[0] */
+	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
+
+	/* FEC TDATA[3] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
+
+	/* FEC TDATA[2] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
+
+	/* FEC TDATA[1] */
+	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
+
+	/* FEC TDATA[0] */
+	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
+
+	/* FEC TX_EN */
+	mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
+
+	/* FEC TX_ER */
+	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
+
+	/* FEC TX_CLK */
+	mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
+
+	/* FEC TX_COL */
+	mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
+
+	/* FEC RX_CLK */
+	mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
+
+	/* FEC RX_CRS */
+	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
+
+	/* FEC RX_ER */
+	mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
+
+	/* FEC RX_DV */
+	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+		*cd = readl(GPIO1_BASE_ADDR) & 0x01;
+	else
+		*cd = readl(GPIO1_BASE_ADDR) & 0x40;
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	u32 index;
+	s32 status = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
+			index++) {
+		switch (index) {
+		case 0:
+			mxc_request_iomux(MX51_PIN_SD1_CMD,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_CLK,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_DATA0,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_DATA1,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_DATA2,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_DATA3,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
+				PAD_CTL_PUE_PULL |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_request_iomux(MX51_PIN_GPIO1_0,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
+				PAD_CTL_HYS_ENABLE);
+			mxc_request_iomux(MX51_PIN_GPIO1_1,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
+				PAD_CTL_HYS_ENABLE);
+			break;
+		case 1:
+			mxc_request_iomux(MX51_PIN_SD2_CMD,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD2_CLK,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD2_DATA0,
+				IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX51_PIN_SD2_DATA1,
+				IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX51_PIN_SD2_DATA2,
+				IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX51_PIN_SD2_DATA3,
+				IOMUX_CONFIG_ALT0);
+			mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
+				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
+				PAD_CTL_SRE_FAST);
+			mxc_request_iomux(MX51_PIN_SD2_CMD,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_GPIO1_6,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
+				PAD_CTL_HYS_ENABLE);
+			mxc_request_iomux(MX51_PIN_GPIO1_5,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
+				PAD_CTL_HYS_ENABLE);
+			break;
+		default:
+			printf("Warning: you configured more ESDHC controller"
+				"(%d) as supported by the board(2)\n",
+				CONFIG_SYS_FSL_ESDHC_NUM);
+			return status;
+		}
+		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+	}
+	return status;
+}
+#endif
+
+int board_init(void)
+{
+	system_rev = get_cpu_rev();
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	setup_iomux_uart();
+	setup_expio();
+	setup_iomux_fec();
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX51EVK ");
+
+	switch (system_rev & 0xff) {
+	case CHIP_REV_3_0:
+		puts("3.0 [");
+		break;
+	case CHIP_REV_2_5:
+		puts("2.5 [");
+		break;
+	case CHIP_REV_2_0:
+		puts("2.0 [");
+		break;
+	case CHIP_REV_1_1:
+		puts("1.1 [");
+		break;
+	case CHIP_REV_1_0:
+	default:
+		puts("1.0 [");
+		break;
+	}
+
+	switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
+	case 0x0001:
+		puts("POR");
+		break;
+	case 0x0009:
+		puts("RST");
+		break;
+	case 0x0010:
+	case 0x0011:
+		puts("WDOG");
+		break;
+	default:
+		puts("unknown");
+	}
+	puts("]\n");
+	return 0;
+}
+
diff --git a/board/voiceblue/eeprom.lds b/board/freescale/mx51evk/mx51evk.h
index 1e48494da54..524cdcced47 100644
--- a/board/voiceblue/eeprom.lds
+++ b/board/freescale/mx51evk/mx51evk.h
@@ -1,8 +1,5 @@
 /*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- * (C) Copyright 2005
- * Ladislav Michl, 2N Telekomunikace, <michl@2n.cz>
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,29 +20,32 @@
  * MA 02111-1307 USA
  */
 
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = ALIGN(4);
-	.text      :
-	{
-	  eeprom_start.o	(.text)
-	  *(.text)
-	}
+#ifndef __BOARD_FREESCALE_MX51_EVK_H__
+#define __BOARD_FREESCALE_MX51_EVK_H__
 
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+#ifndef __ASSEMBLY__
+struct io_board_ctrl {
+	u16 led_ctrl;		/* 0x00 */
+	u16 resv1[0x03];
+	u16 sb_stat;		/* 0x08 */
+	u16 resv2[0x03];
+	u16 int_stat;		/* 0x10 */
+	u16 resv3[0x07];
+	u16 int_rest;		/* 0x20 */
+	u16 resv4[0x0B];
+	u16 int_mask;		/* 0x38 */
+	u16 resv5[0x03];
+	u16 id1;		/* 0x40 */
+	u16 resv6[0x03];
+	u16 id2;		/* 0x48 */
+	u16 resv7[0x03];
+	u16 version;		/* 0x50 */
+	u16 resv8[0x03];
+	u16 id3;		/* 0x58 */
+	u16 resv9[0x03];
+	u16 sw_reset;		/* 0x60 */
+};
+#endif
 
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
-	_end = .;
-}
+#define IO_BOARD_OFFSET		(0x20000)
+#endif
diff --git a/board/exbitgen/Makefile b/board/karo/tx25/Makefile
index 4f752a86b45..b0e610fc352 100644
--- a/board/exbitgen/Makefile
+++ b/board/karo/tx25/Makefile
@@ -1,6 +1,6 @@
 #
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2009 DENX Software Engineering
+# Author: John Rigby <jcrigby@gmail.com>
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -25,16 +25,15 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o
-
-SOBJS	= init.o
+COBJS	:= tx25.o
+SOBJS	:= lowlevel_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $^
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
 clean:
 	rm -f $(SOBJS) $(OBJS)
@@ -44,9 +43,9 @@ distclean:	clean
 
 #########################################################################
 
-# defines $(obj).depend target
 include $(SRCTREE)/rules.mk
 
 sinclude $(obj).depend
 
 #########################################################################
+
diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk
new file mode 100644
index 00000000000..732a14a6d1e
--- /dev/null
+++ b/board/karo/tx25/config.mk
@@ -0,0 +1,5 @@
+ifdef CONFIG_NAND_SPL
+TEXT_BASE = 0x81ec0000
+else
+TEXT_BASE = 0x81f00000
+endif
diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S
new file mode 100644
index 00000000000..823df10701e
--- /dev/null
+++ b/board/karo/tx25/lowlevel_init.S
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on U-Boot and RedBoot sources for several different i.mx
+ * platforms.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/macro.h>
+
+.macro init_aips
+	write32	0x43f00000, 0x77777777
+	write32	0x43f00004, 0x77777777
+	write32	0x43f00000, 0x77777777
+	write32	0x53f00004, 0x77777777
+.endm
+
+.macro init_max
+	write32	0x43f04000, 0x43210
+	write32	0x43f04100, 0x43210
+	write32	0x43f04200, 0x43210
+	write32	0x43f04300, 0x43210
+	write32	0x43f04400, 0x43210
+
+	write32	0x43f04010, 0x10
+	write32	0x43f04110, 0x10
+	write32	0x43f04210, 0x10
+	write32	0x43f04310, 0x10
+	write32	0x43f04410, 0x10
+
+	write32	0x43f04800, 0x0
+	write32	0x43f04900, 0x0
+	write32	0x43f04a00, 0x0
+	write32	0x43f04b00, 0x0
+	write32	0x43f04c00, 0x0
+.endm
+
+.macro init_m3if
+	write32 0xb8003000, 0x1
+.endm
+
+.macro init_clocks
+	/*
+	 * clocks
+	 *
+	 * first enable CLKO debug output
+	 * 0x40000000 enables the debug CLKO signal
+	 * 0x05000000 sets CLKO divider to 6
+	 * 0x00600000 makes CLKO parent clk the USB clk
+	 */
+	write32	0x53f80064, 0x45600000
+	write32	0x53f80008, 0x20034000
+
+	/*
+	 * enable all implemented clocks in all three
+	 * clock control registers
+	 */
+	write32	0x53f8000c, 0x1fffffff
+	write32	0x53f80010, 0xffffffff
+	write32	0x53f80014, 0xfdfff
+.endm
+
+.macro init_ddrtype
+	/*
+	 * ddr_type is 3.3v SDRAM
+	 */
+	write32	0x43fac454, 0x800
+.endm
+
+/*
+ * sdram controller init
+ */
+.macro init_sdram_bank bankaddr, ctl, cfg
+	ldr	r0, =0xb8001000
+	ldr	r2, =\bankaddr
+	/*
+	 * reset SDRAM controller
+	 * then wait for initialization to complete
+	 */
+	ldr	r1, =(1 << 1)
+	str	r1, [r0, #0x10]
+1:	ldr	r3, [r0, #0x10]
+	tst	r3, #(1 << 31)
+	beq	1b
+
+	ldr	r1, =0x95728
+	str	r1, [r0, #\cfg]		/* config */
+
+	ldr	r1, =0x92116480		/* control | precharge */
+	str	r1, [r0, #\ctl]		/* write command to controller */
+	str	r1, [r2, #0x400]	/* command encoded in address */
+
+	ldr	r1, =0xa2116480		/* auto refresh */
+	str	r1, [r0, #\ctl]
+	ldrb	r3, [r2]		/* read dram twice to auto refresh */
+	ldrb	r3, [r2]
+
+	ldr	r1, =0xb2116480		/* control | load mode */
+	str	r1, [r0, #\ctl]		/* write command to controller */
+	strb	r1, [r2, #0x33]		/* command encoded in address */
+
+	ldr	r1, =0x82116480		/* control  | normal (0)*/
+	str	r1, [r0, #\ctl]		/* write command to controller */
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+	init_aips
+	init_max
+	init_m3if
+	init_clocks
+
+	init_sdram_bank 0x80000000, 0x0, 0x4
+
+	init_sdram_bank 0x90000000, 0x8, 0xc
+	mov	pc, lr
diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c
new file mode 100644
index 00000000000..4d6a96d20e3
--- /dev/null
+++ b/board/karo/tx25/tx25.c
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on imx27lite.c:
+ *   Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ *   Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ * And:
+ *   RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/imx25-pinmux.h>
+
+static void mdelay(int n)
+{
+	while (n-- > 0)
+		udelay(1000);
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FEC_MXC
+void tx25_fec_init(void)
+{
+	struct iomuxc_mux_ctl *muxctl;
+	struct iomuxc_pad_ctl *padctl;
+	u32 val;
+	u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+	struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE;
+	struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE;
+	u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode;
+
+	debug("tx25_fec_init\n");
+	/*
+	 * fec pin init is generic
+	 */
+	mx25_fec_init_pins();
+
+	/*
+	 * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
+	 *
+	 * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13
+	 * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11
+	 */
+	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+
+	writel(gpio_mux_mode, &muxctl->pad_d13);
+	writel(gpio_mux_mode, &muxctl->pad_d11);
+
+	writel(0x0, &padctl->pad_d13);
+	writel(0x0, &padctl->pad_d11);
+
+	/* drop PHY power and assert reset (low) */
+	val = readl(&gpio4->dr) & ~((1 << 7) | (1 << 9));
+	writel(val, &gpio4->dr);
+	val = readl(&gpio4->dir) | (1 << 7) | (1 << 9);
+	writel(val, &gpio4->dir);
+
+	mdelay(5);
+
+	debug("resetting phy\n");
+
+	/* turn on PHY power leaving reset asserted */
+	val = readl(&gpio4->dr) | 1 << 9;
+	writel(val, &gpio4->dr);
+
+	mdelay(10);
+
+	/*
+	 * Setup some strapping pins that are latched by the PHY
+	 * as reset goes high.
+	 *
+	 * Set PHY mode to 111
+	 *  mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5
+	 *  mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5
+	 *  mode2 is tied high so nothing to do
+	 *
+	 * Turn on RMII mode
+	 *  RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
+	 */
+	/*
+	 * save three current mux modes and set each to gpio mode
+	 */
+	saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0);
+	saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1);
+	saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv);
+
+	writel(gpio_mux_mode, &muxctl->pad_fec_rdata0);
+	writel(gpio_mux_mode, &muxctl->pad_fec_rdata1);
+	writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv);
+
+	/*
+	 * set each to 1 and make each an output
+	 */
+	val = readl(&gpio3->dr) | (1 << 10) | (1 << 11) | (1 << 12);
+	writel(val, &gpio3->dr);
+	val = readl(&gpio3->dir) | (1 << 10) | (1 << 11) | (1 << 12);
+	writel(val, &gpio3->dir);
+
+	mdelay(22);		/* this value came from RedBoot */
+
+	/*
+	 * deassert PHY reset
+	 */
+	val = readl(&gpio4->dr) | 1 << 7;
+	writel(val, &gpio4->dr);
+	writel(val, &gpio4->dr);
+
+	mdelay(5);
+
+	/*
+	 * set FEC pins back
+	 */
+	writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0);
+	writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1);
+	writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv);
+}
+#else
+#define tx25_fec_init()
+#endif
+
+int board_init()
+{
+#ifdef CONFIG_MXC_UART
+	extern void mx25_uart_init_pins(void);
+
+	mx25_uart_init_pins();
+#endif
+	return 0;
+}
+
+int board_late_init(void)
+{
+	tx25_fec_init();
+	return 0;
+}
+
+int dram_init (void)
+{
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+			PHYS_SDRAM_1_SIZE);
+#if CONFIG_NR_DRAM_BANKS > 1
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+			PHYS_SDRAM_2_SIZE);
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("KARO TX25\n");
+	return 0;
+}
diff --git a/board/kb9202/kb9202.c b/board/kb9202/kb9202.c
index 59ed8ff6042..3164cc5ac44 100644
--- a/board/kb9202/kb9202.c
+++ b/board/kb9202/kb9202.c
@@ -28,8 +28,12 @@
 
 #include <common.h>
 #include <asm/arch/AT91RM9200.h>
+#include <asm/io.h>
+#include <netdev.h>
+#if defined(CONFIG_DRIVER_ETHER)
 #include <at91rm9200_net.h>
 #include <lxt971a.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -92,3 +96,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
 
 #endif
 #endif	/* CONFIG_DRIVER_ETHER */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index ec27bdae223..7b4eefd5c82 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -35,6 +35,7 @@
 #include <libfdt.h>
 #endif
 
+#include "../common/common.h"
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
 #include <i2c.h>
 
@@ -421,7 +422,6 @@ static int get_scl (void)
 
 	return ((val & SCL_BIT) == SCL_BIT);
 }
-
 #endif
 
 #if !defined(CONFIG_KMETER1)
@@ -500,7 +500,7 @@ void i2c_init_board(void)
 	out_8 (&dev->cr, (I2C_CR_MEN));
 
 #else
-#if defined(CONFIG_HARD_I2C)
+#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_MACH_SUEN3)
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
 	volatile i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
 
@@ -578,10 +578,12 @@ int fdt_get_node_and_value (void *blob,
 }
 #endif
 
+#if !defined(CONFIG_MACH_SUEN3)
 int ethernet_present (void)
 {
 	return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80);
 }
+#endif
 
 int board_eth_init (bd_t *bis)
 {
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
new file mode 100644
index 00000000000..c5b0be16ef7
--- /dev/null
+++ b/board/keymile/km_arm/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o ../common/common.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/keymile/km_arm/config.mk b/board/keymile/km_arm/config.mk
new file mode 100644
index 00000000000..b9e81b26bb6
--- /dev/null
+++ b/board/keymile/km_arm/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x004000000
+
+# Kirkwood Boot Image configuration file
+KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
new file mode 100644
index 00000000000..53cf474767c
--- /dev/null
+++ b/board/keymile/km_arm/km_arm.c
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <nand.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int	io_dev;
+extern I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
+
+/* Multi-Purpose Pins Functionality configuration */
+u32 kwmpp_config[] = {
+	MPP0_NF_IO2,
+	MPP1_NF_IO3,
+	MPP2_NF_IO4,
+	MPP3_NF_IO5,
+	MPP4_NF_IO6,
+	MPP5_NF_IO7,
+	MPP6_SYSRST_OUTn,
+	MPP7_PEX_RST_OUTn,
+#if defined(CONFIG_SOFT_I2C)
+	MPP8_GPIO,		/* SDA */
+	MPP9_GPIO,		/* SCL */
+#endif
+#if defined(CONFIG_HARD_I2C)
+	MPP8_TW_SDA,
+	MPP9_TW_SCK,
+#endif
+	MPP10_UART0_TXD,
+	MPP11_UART0_RXD,
+	MPP12_GPO,		/* Reserved */
+	MPP13_UART1_TXD,
+	MPP14_UART1_RXD,
+	MPP15_GPIO,		/* Not used */
+	MPP16_GPIO,		/* Not used */
+	MPP17_GPIO,		/* Reserved */
+	MPP18_NF_IO0,
+	MPP19_NF_IO1,
+	MPP20_GPIO,
+	MPP21_GPIO,
+	MPP22_GPIO,
+	MPP23_GPIO,
+	MPP24_GPIO,
+	MPP25_GPIO,
+	MPP26_GPIO,
+	MPP27_GPIO,
+	MPP28_GPIO,
+	MPP29_GPIO,
+	MPP30_GPIO,
+	MPP31_GPIO,
+	MPP32_GPIO,
+	MPP33_GPIO,
+	MPP34_GPIO,		/* CDL1 (input) */
+	MPP35_GPIO,		/* CDL2 (input) */
+	MPP36_GPIO,		/* MAIN_IRQ (input) */
+	MPP37_GPIO,		/* BOARD_LED */
+	MPP38_GPIO,		/* Piggy3 LED[1] */
+	MPP39_GPIO,		/* Piggy3 LED[2] */
+	MPP40_GPIO,		/* Piggy3 LED[3] */
+	MPP41_GPIO,		/* Piggy3 LED[4] */
+	MPP42_GPIO,		/* Piggy3 LED[5] */
+	MPP43_GPIO,		/* Piggy3 LED[6] */
+	MPP44_GPIO,		/* Piggy3 LED[7] */
+	MPP45_GPIO,		/* Piggy3 LED[8] */
+	MPP46_GPIO,		/* Reserved */
+	MPP47_GPIO,		/* Reserved */
+	MPP48_GPIO,		/* Reserved */
+	MPP49_GPIO,		/* SW_INTOUTn */
+	0
+};
+
+int ethernet_present(void)
+{
+	uchar	buf;
+	int	ret = 0;
+
+	if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
+		printf ("%s: Error reading Boco\n", __FUNCTION__);
+		return -1;
+	}
+	if ((buf & 0x40) == 0x40) {
+		ret = 1;
+	}
+	return ret;
+}
+
+int misc_init_r(void)
+{
+	I2C_MUX_DEVICE	*i2cdev;
+	char *str;
+	int mach_type;
+
+	/* add I2C Bus for I/O Expander */
+	i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a");
+	io_dev = i2cdev->busid;
+	puts("Piggy:");
+	if (ethernet_present() == 0)
+		puts (" not");
+	puts(" present\n");
+
+	str = getenv("mach_type");
+	if (str != NULL) {
+		mach_type = simple_strtoul(str, NULL, 10);
+		printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
+		gd->bd->bi_arch_number = mach_type;
+	}
+	return 0;
+}
+
+int board_init(void)
+{
+	u32 tmp;
+
+	kirkwood_mpp_conf(kwmpp_config);
+
+	/*
+	 * The FLASH_GPIO_PIN switches between using a
+	 * NAND or a SPI FLASH. Set this pin on start
+	 * to NAND mode.
+	 */
+	tmp = readl(KW_GPIO0_BASE);
+	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
+	tmp = readl(KW_GPIO0_BASE + 4);
+	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
+	printf("KM: setting NAND mode\n");
+
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+#if defined(CONFIG_SOFT_I2C)
+	/* init the GPIO for I2C Bitbang driver */
+	kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
+	kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
+	kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
+	kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
+#endif
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	kw_gpio_set_valid(SUEN3_ENV_WP, 38);
+	kw_gpio_direction_output(SUEN3_ENV_WP, 1);
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_CMD_SF)
+int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 tmp;
+	if (argc < 2) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	if ((strcmp(argv[1], "off") == 0)) {
+		printf("SPI FLASH disabled, NAND enabled\n");
+		/* Multi-Purpose Pins Functionality configuration */
+		kwmpp_config[0] = MPP0_NF_IO2;
+		kwmpp_config[1] = MPP1_NF_IO3;
+		kwmpp_config[2] = MPP2_NF_IO4;
+		kwmpp_config[3] = MPP3_NF_IO5;
+
+		kirkwood_mpp_conf(kwmpp_config);
+		tmp = readl(KW_GPIO0_BASE);
+		writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
+	} else if ((strcmp(argv[1], "on") == 0)) {
+		printf("SPI FLASH enabled, NAND disabled\n");
+		/* Multi-Purpose Pins Functionality configuration */
+		kwmpp_config[0] = MPP0_SPI_SCn;
+		kwmpp_config[1] = MPP1_SPI_MOSI;
+		kwmpp_config[2] = MPP2_SPI_SCK;
+		kwmpp_config[3] = MPP3_SPI_MISO;
+
+		kirkwood_mpp_conf(kwmpp_config);
+		tmp = readl(KW_GPIO0_BASE);
+		writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
+	} else {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	spitoggle,	2,	0,	do_spi_toggle,
+	"En-/disable SPI FLASH access",
+	"<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
+	);
+#endif
+
+int dram_init(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+		gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
+						       kw_sdram_bs(i));
+	}
+	return 0;
+}
+
+/* Configure and enable MV88E1118 PHY */
+void reset_phy(void)
+{
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* reset the phy */
+	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
+}
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var (void)
+{
+	ivm_read_eeprom ();
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
+void bootcount_store (ulong a)
+{
+	volatile ulong *save_addr;
+	volatile ulong size = 0;
+	int i;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		size += gd->bd->bi_dram[i].size;
+	}
+	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
+	writel(a, save_addr);
+	writel(BOOTCOUNT_MAGIC, &save_addr[1]);
+}
+
+ulong bootcount_load (void)
+{
+	volatile ulong *save_addr;
+	volatile ulong size = 0;
+	int i;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		size += gd->bd->bi_dram[i].size;
+	}
+	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
+	if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
+		return 0;
+	else
+		return readl(save_addr);
+}
+#endif
+
+#if defined(CONFIG_SOFT_I2C)
+void set_sda (int state)
+{
+	I2C_ACTIVE;
+	I2C_SDA(state);
+}
+
+void set_scl (int state)
+{
+	I2C_SCL(state);
+}
+
+int get_sda (void)
+{
+	I2C_TRISTATE;
+	return I2C_READ;
+}
+
+int get_scl (void)
+{
+	return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0);
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	kw_gpio_set_value(SUEN3_ENV_WP, !state);
+
+	return !kw_gpio_get_value(SUEN3_ENV_WP);
+}
+#endif
diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg
new file mode 100644
index 00000000000..26d6aa09d97
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage.cfg
@@ -0,0 +1,175 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01111111	# MPP Control 0 Register
+# bit 3-0:   MPPSel0	1, NF_IO[2]
+# bit 7-4:   MPPSel1	1, NF_IO[3]
+# bit 12-8:  MPPSel2	1, NF_IO[4]
+# bit 15-12: MPPSel3	1, NF_IO[5]
+# bit 19-16: MPPSel4	1, NF_IO[6]
+# bit 23-20: MPPSel5	1, NF_IO[7]
+# bit 27-24: MPPSel6	1, SYSRST_O
+# bit 31-28: MPPSel7	0, GPO[7]
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   MPPSel16	0, GPIO[16]
+# bit 7-4:   MPPSel17	0, GPIO[17]
+# bit 12-8:  MPPSel18	1, NF_IO[0]
+# bit 15-12: MPPSel19	1, NF_IO[1]
+# bit 19-16: MPPSel20	0, GPIO[20]
+# bit 23-20: MPPSel21	0, GPIO[21]
+# bit 27-24: MPPSel22	0, GPIO[22]
+# bit 31-28: MPPSel23	0, GPIO[23]
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+DATA 0xFFD20134 0xBBBBBBBB	# L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x00BBBBBB	# L2 RAM Timing 1 Register
+DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
+DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
+DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+
+#Dram initalization
+DATA 0xFFD01400 0x43000400	# SDRAM Configuration Register
+# bit13-0:  0x400 (DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x36343000	# DDR Controller Control Low
+# bit 3-0:  0 reserved
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302544B	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000032	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000D	#  DDR Address Control
+# bit1-0:   01, Cs0width=x16
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000642	#  DDR Mode
+DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    1,  DDR ODT control lsd disabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  0  , no sample stage
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00000000	#  DDR ODT Control (Low)
+# bit3-0:  0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  00, ODT1 controlled by register
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E90F	# CPU ODT Control
+# bit3-0:  F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit9-8:  1, ODTEn, never active
+# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/m501sk/m501sk.c b/board/m501sk/m501sk.c
index 1e6a6056722..c9957684b18 100644
--- a/board/m501sk/m501sk.c
+++ b/board/m501sk/m501sk.c
@@ -24,8 +24,13 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#if defined(CONFIG_DRIVER_ETHER)
 #include <at91rm9200_net.h>
 #include <dm9161.h>
+#endif
+
 #include "m501sk.h"
 #include "net.h"
 
@@ -186,4 +191,13 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
 }
 #endif /* CONFIG_CMD_NET */
 #endif /* CONFIG_DRIVER_ETHER */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
 #endif /* CONFIG_M501SK */
diff --git a/board/mp2usb/mp2usb.c b/board/mp2usb/mp2usb.c
index dcda699dc87..e5eba6bbc09 100644
--- a/board/mp2usb/mp2usb.c
+++ b/board/mp2usb/mp2usb.c
@@ -27,8 +27,12 @@
 
 #include <common.h>
 #include <asm/arch/AT91RM9200.h>
+#include <netdev.h>
+#include <asm/io.h>
+#if defined(CONFIG_DRIVER_ETHER)
 #include <at91rm9200_net.h>
 #include <dm9161.h>
+#endif
 #include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -83,3 +87,12 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
 
 #endif
 #endif	/* CONFIG_DRIVER_ETHER */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = at91emac_register(bis, 0);
+	return rc;
+}
+#endif
diff --git a/board/netstar/Makefile b/board/netstar/Makefile
index 11578b7f3df..c435762964f 100644
--- a/board/netstar/Makefile
+++ b/board/netstar/Makefile
@@ -29,20 +29,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= netstar.o
-SOBJS	:= setup.o crcek.o
+SOBJS	:= setup.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c \
-		eeprom_start.S
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
-
 LOAD_ADDR = 0x10400000
-LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
-lnk = $(if $(obj),$(obj),.)
 
-HOSTCFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+#########################################################################
 
 all:	$(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \
 		$(obj)crcek.srec $(obj)crcek.bin $(obj)crcit
@@ -50,41 +45,42 @@ all:	$(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $^
 
-$(obj)eeprom.srec:	$(obj)eeprom.o $(obj)eeprom_start.o $(obj)u-boot.lds
-	cd $(lnk) && $(LD) -T $(obj)u-boot.lds -g -Ttext $(LOAD_ADDR) \
-		-o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \
+$(obj)eeprom_start.o:
+	echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ -
+
+$(obj)eeprom:		$(obj)eeprom_start.o $(obj)eeprom.o
+	$(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \
 		-L$(obj)../../examples/standalone -lstubs \
-		-L$(obj)../../lib_generic -lgeneric \
-		-L$(gcclibdir) -lgcc
-	$(OBJCOPY) -O srec $(<:.o=) $@
+		$(PLATFORM_LIBS)
 
-$(obj)eeprom.bin:	$(obj)eeprom.srec
-	$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
+$(obj)eeprom.srec:	$(obj)eeprom
+	$(OBJCOPY) -S -O srec $(<:.o=) $@
+
+$(obj)eeprom.bin:	$(obj)eeprom
+	$(OBJCOPY) -S -O binary $< $@
 
 $(obj)crcek.srec:	$(obj)crcek.o
-	$(LD) -g -Ttext 0x00000000 \
-		-o $(<:.o=) -e crcek $^
-	$(OBJCOPY) -O srec $(<:.o=) $@
+	$(LD) -g -Ttext 0x00000000 -e crcek -o $(<:.o=) $^
+	$(OBJCOPY) -S -O srec $(<:.o=) $@
 
 $(obj)crcek.bin:	$(obj)crcek.srec
-	$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
+	$(OBJCOPY) -I srec -O binary $< $@
 
 $(obj)crcit:		$(obj)crcit.o $(obj)crc32.o
 	$(HOSTCC) $(HOSTCFLAGS) -o $@ $^
 
-$(obj)crcit.o:	crcit.c
+$(obj)crcit.o:		crcit.c
 	$(HOSTCC) $(HOSTCFLAGS) -o $@ -c $<
 
-$(obj)crc32.o:	$(SRCTREE)/lib_generic/crc32.c
-	$(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -o $@ -c $<
-
-$(obj)u-boot.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+$(obj)crc32.o:		$(SRCTREE)/lib_generic/crc32.c
+	$(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -I$(TOPDIR)/include \
+		-o $@ -c $<
 
 clean:
-	rm -f $(SOBJS) $(OBJS) $(obj)eeprom $(obj)eeprom.srec \
-		$(obj)eeprom.bin $(obj)crcek $(obj)crcek.srec \
-		$(obj)crcek.bin $(obj)u-boot.lds
+	rm -f $(SOBJS) $(OBJS) \
+		$(obj)eeprom_start.o $(obj)eeprom.o \
+		$(obj)eeprom $(obj)eeprom.srec 	$(obj)eeprom.bin \
+		$(obj)crcek.o $(obj)crcek $(obj)crcek.srec $(obj)crcek.bin
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c
index adb01b96b89..aca4458e29b 100644
--- a/board/netstar/eeprom.c
+++ b/board/netstar/eeprom.c
@@ -28,67 +28,76 @@
 #include <net.h>
 #include "../drivers/net/smc91111.h"
 
-static u16 read_eeprom_reg(struct eth_device *dev, u16 reg)
+static struct eth_device dev = {
+	.iobase = CONFIG_SMC91111_BASE
+};
+
+static u16 read_eeprom_reg(u16 reg)
 {
 	int timeout;
 
-	SMC_SELECT_BANK(dev, 2);
-	SMC_outw(dev, reg, PTR_REG);
+	SMC_SELECT_BANK(&dev, 2);
+	SMC_outw(&dev, reg, PTR_REG);
+
+	SMC_SELECT_BANK(&dev, 1);
+	SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
+		CTL_RELOAD, CTL_REG);
 
-	SMC_SELECT_BANK(dev, 1);
-	SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
-		 CTL_REG);
 	timeout = 100;
-	while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
+
+	while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout)
 		udelay(100);
 	if (timeout == 0) {
-		printf("Timeout Reading EEPROM register %02x\n", reg);
+		printf("Timeout reading register %02x\n", reg);
 		return 0;
 	}
 
-	return SMC_inw (dev, GP_REG);
+	return SMC_inw(&dev, GP_REG);
 }
 
-static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg)
+static int write_eeprom_reg(u16 value, u16 reg)
 {
 	int timeout;
 
-	SMC_SELECT_BANK(dev, 2);
-	SMC_outw(dev, reg, PTR_REG);
+	SMC_SELECT_BANK(&dev, 2);
+	SMC_outw(&dev, reg, PTR_REG);
+
+	SMC_SELECT_BANK(&dev, 1);
+
+	SMC_outw(&dev, value, GP_REG);
+	SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
+		CTL_STORE, CTL_REG);
 
-	SMC_SELECT_BANK(dev, 1);
-	SMC_outw(dev, value, GP_REG);
-	SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
 	timeout = 100;
-	while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout)
-		udelay (100);
+
+	while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout)
+		udelay(100);
 	if (timeout == 0) {
-		printf("Timeout Writing EEPROM register %02x\n", reg);
+		printf("Timeout writing register %02x\n", reg);
 		return 0;
 	}
 
 	return 1;
 }
 
-static int write_data(struct eth_device *dev, u16 *buf, int len)
+static int write_data(u16 *buf, int len)
 {
 	u16 reg = 0x23;
 
 	while (len--)
-		write_eeprom_reg(dev, *buf++, reg++);
+		write_eeprom_reg(*buf++, reg++);
 
 	return 0;
 }
 
-static int verify_macaddr(struct eth_device *dev, char *s)
+static int verify_macaddr(char *s)
 {
 	u16 reg;
 	int i, err = 0;
 
-	printf("MAC Address: ");
-	err = i = 0;
+	puts("HWaddr: ");
 	for (i = 0; i < 3; i++) {
-		reg = read_eeprom_reg(dev, 0x20 + i);
+		reg = read_eeprom_reg(0x20 + i);
 		printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
 		if (s)
 			err |= reg != ((u16 *)s)[i];
@@ -97,7 +106,7 @@ static int verify_macaddr(struct eth_device *dev, char *s)
 	return err ? 0 : 1;
 }
 
-static int set_mac(struct eth_device *dev, char *s)
+static int set_mac(char *s)
 {
 	int i;
 	char *e, eaddr[6];
@@ -109,7 +118,7 @@ static int set_mac(struct eth_device *dev, char *s)
 	}
 
 	for (i = 0; i < 3; i++)
-		write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i);
+		write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
 
 	return 0;
 }
@@ -145,34 +154,30 @@ int eeprom(int argc, char *argv[])
 	int i, len, ret;
 	unsigned char buf[58], *p;
 
-	struct eth_device dev = {
-		.iobase = CONFIG_SMC91111_BASE
-	};
-
 	app_startup(argv);
-	if (get_version() != XF_VERSION) {
-		printf("Wrong XF_VERSION.\n");
-		printf("Application expects ABI version %d\n", XF_VERSION);
-		printf("Actual U-Boot ABI version %d\n", (int)get_version());
+	i = get_version();
+	if (i != XF_VERSION) {
+		printf("Using ABI version %d, but U-Boot provides %d\n",
+			XF_VERSION, i);
 		return 1;
 	}
 
-	if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
-		printf("SMSC91111 not found.\n");
+	if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
+		puts("SMSC91111 not found\n");
 		return 2;
 	}
 
 	/* Called without parameters - print MAC address */
 	if (argc < 2) {
-		verify_macaddr(&dev, NULL);
+		verify_macaddr(NULL);
 		return 0;
 	}
 
 	/* Print help message */
 	if (argv[1][1] == 'h') {
-		printf("NetStar EEPROM writer\n");
-		printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
-		printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
+		puts("NetStar EEPROM writer\n"
+			"Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n"
+			"Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
 		return 0;
 	}
 
@@ -189,7 +194,7 @@ int eeprom(int argc, char *argv[])
 			printf("Element %d: odd character count\n", i - 1);
 			return 3;
 		case -3:
-			printf("Out of EEPROM memory\n");
+			puts("Out of EEPROM memory\n");
 			return 3;
 		default:
 			p += ret;
@@ -198,16 +203,16 @@ int eeprom(int argc, char *argv[])
 	}
 
 	/* First argument (MAC) is mandatory */
-	set_mac(&dev, argv[1]);
-	if (verify_macaddr(&dev, argv[1])) {
-		printf("*** MAC address does not match! ***\n");
+	set_mac(argv[1]);
+	if (verify_macaddr(argv[1])) {
+		puts("*** HWaddr does not match! ***\n");
 		return 4;
 	}
 
 	while (len--)
 		*p++ = 0;
 
-	write_data(&dev, (u16 *)buf, sizeof(buf) >> 1);
+	write_data((u16 *)buf, sizeof(buf) >> 1);
 
 	return 0;
 }
diff --git a/board/netstar/eeprom.lds b/board/netstar/eeprom.lds
deleted file mode 100644
index 1e48494da54..00000000000
--- a/board/netstar/eeprom.lds
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- * (C) Copyright 2005
- * Ladislav Michl, 2N Telekomunikace, <michl@2n.cz>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = ALIGN(4);
-	.text      :
-	{
-	  eeprom_start.o	(.text)
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
-	_end = .;
-}
diff --git a/board/netstar/eeprom_start.S b/board/netstar/eeprom_start.S
deleted file mode 100644
index 3609382ad83..00000000000
--- a/board/netstar/eeprom_start.S
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2005  2N Telekomunikace
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- */
-
-.globl _start
-_start:	b	eeprom
-
-.end
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index 6915b9b2b3d..8662339581f 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -189,7 +189,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2009 Ronetix GmbH\n");
 	lcd_printf ("support@ronetix.at\n");
 	lcd_printf ("%s CPU at %s MHz",
-		AT91_CPU_NAME,
+		CONFIG_SYS_AT91_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 29555f8db32..23ea154b435 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -304,7 +304,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2009 Ronetix GmbH\n");
 	lcd_printf ("support@ronetix.at\n");
 	lcd_printf ("%s CPU at %s MHz",
-		AT91_CPU_NAME,
+		CONFIG_SYS_AT91_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
index 756aa563975..03dfe16175e 100755
--- a/board/spear/spear310/spear310.c
+++ b/board/spear/spear310/spear310.c
@@ -32,7 +32,7 @@
 
 int board_init(void)
 {
-	return spear_board_init(MACH_TYPE_SPEAR300);
+	return spear_board_init(MACH_TYPE_SPEAR310);
 }
 
 /*
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
index 756aa563975..2ba2dbb5666 100755
--- a/board/spear/spear320/spear320.c
+++ b/board/spear/spear320/spear320.c
@@ -32,7 +32,7 @@
 
 int board_init(void)
 {
-	return spear_board_init(MACH_TYPE_SPEAR300);
+	return spear_board_init(MACH_TYPE_SPEAR320);
 }
 
 /*
diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile
index 121c717d9db..0067f056376 100644
--- a/board/voiceblue/Makefile
+++ b/board/voiceblue/Makefile
@@ -29,40 +29,37 @@ LIB	= $(obj)lib$(BOARD).a
 COBJS	:= voiceblue.o
 SOBJS	:= setup.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c eeprom_start.S
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
-
 LOAD_ADDR = 0x10400000
-LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
-lnk = $(if $(obj),$(obj),.)
+
+#########################################################################
 
 all:	$(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin
 
 $(LIB):	$(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $^
+
+$(obj)eeprom_start.o:
+	echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ -
 
-$(obj)eeprom.srec:	$(obj)eeprom.o $(obj)eeprom_start.o $(obj)u-boot.lds
-	cd $(lnk) && $(LD) -T $(obj)u-boot.lds -g -Ttext $(LOAD_ADDR) \
-		-o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \
+$(obj)eeprom:		$(obj)eeprom_start.o $(obj)eeprom.o
+	$(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \
 		-L$(obj)../../examples/standalone -lstubs \
-		-L$(obj)../../lib_generic -lgeneric \
-		-L$(gcclibdir) -lgcc
-	$(OBJCOPY) -O srec $(<:.o=) $@
+		$(PLATFORM_LIBS)
 
-$(obj)eeprom.bin:	$(obj)eeprom.srec
-	$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
+$(obj)eeprom.srec:	$(obj)eeprom
+	$(OBJCOPY) -S -O srec $(<:.o=) $@
 
-$(obj)u-boot.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+$(obj)eeprom.bin:	$(obj)eeprom
+	$(OBJCOPY) -S -O binary $< $@
 
 clean:
 	rm -f $(SOBJS) $(OBJS) $(obj)eeprom \
 		$(obj)eeprom.srec $(obj)eeprom.bin \
-		$(obj)eeprom.o $(obj)eeprom_start.o \
-		 $(obj)u-boot.lds
+		$(obj)eeprom.o $(obj)eeprom_start.o
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c
index 2ae46d10cd7..f7e0ba56abb 100644
--- a/board/voiceblue/eeprom.c
+++ b/board/voiceblue/eeprom.c
@@ -22,75 +22,82 @@
  * Some code shamelessly stolen back from Robin Getz.
  */
 
-#define DEBUG
-
 #include <common.h>
 #include <exports.h>
 #include <timestamp.h>
 #include <net.h>
 #include "../drivers/net/smc91111.h"
 
-static u16 read_eeprom_reg(struct eth_device *dev, u16 reg)
+static struct eth_device dev = {
+	.iobase = CONFIG_SMC91111_BASE
+};
+
+static u16 read_eeprom_reg(u16 reg)
 {
 	int timeout;
 
-	SMC_SELECT_BANK(dev, 2);
-	SMC_outw(dev, reg, PTR_REG);
+	SMC_SELECT_BANK(&dev, 2);
+	SMC_outw(&dev, reg, PTR_REG);
+
+	SMC_SELECT_BANK(&dev, 1);
+	SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
+		CTL_RELOAD, CTL_REG);
 
-	SMC_SELECT_BANK(dev, 1);
-	SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
-		 CTL_REG);
 	timeout = 100;
-	while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
+
+	while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout)
 		udelay(100);
 	if (timeout == 0) {
-		printf("Timeout Reading EEPROM register %02x\n", reg);
+		printf("Timeout reading register %02x\n", reg);
 		return 0;
 	}
 
-	return SMC_inw (dev, GP_REG);
+	return SMC_inw(&dev, GP_REG);
 }
 
-static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg)
+static int write_eeprom_reg(u16 value, u16 reg)
 {
 	int timeout;
 
-	SMC_SELECT_BANK(dev, 2);
-	SMC_outw(dev, reg, PTR_REG);
+	SMC_SELECT_BANK(&dev, 2);
+	SMC_outw(&dev, reg, PTR_REG);
+
+	SMC_SELECT_BANK(&dev, 1);
+
+	SMC_outw(&dev, value, GP_REG);
+	SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
+		CTL_STORE, CTL_REG);
 
-	SMC_SELECT_BANK(dev, 1);
-	SMC_outw(dev, value, GP_REG);
-	SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
 	timeout = 100;
-	while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout)
-		udelay (100);
+
+	while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout)
+		udelay(100);
 	if (timeout == 0) {
-		printf("Timeout Writing EEPROM register %02x\n", reg);
+		printf("Timeout writing register %02x\n", reg);
 		return 0;
 	}
 
 	return 1;
 }
 
-static int write_data(struct eth_device *dev, u16 *buf, int len)
+static int write_data(u16 *buf, int len)
 {
 	u16 reg = 0x23;
 
 	while (len--)
-		write_eeprom_reg(dev, *buf++, reg++);
+		write_eeprom_reg(*buf++, reg++);
 
 	return 0;
 }
 
-static int verify_macaddr(struct eth_device *dev, char *s)
+static int verify_macaddr(char *s)
 {
 	u16 reg;
 	int i, err = 0;
 
-	printf("MAC Address: ");
-	err = i = 0;
+	puts("HWaddr: ");
 	for (i = 0; i < 3; i++) {
-		reg = read_eeprom_reg(dev, 0x20 + i);
+		reg = read_eeprom_reg(0x20 + i);
 		printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
 		if (s)
 			err |= reg != ((u16 *)s)[i];
@@ -99,7 +106,7 @@ static int verify_macaddr(struct eth_device *dev, char *s)
 	return err ? 0 : 1;
 }
 
-static int set_mac(struct eth_device *dev, char *s)
+static int set_mac(char *s)
 {
 	int i;
 	char *e, eaddr[6];
@@ -111,7 +118,7 @@ static int set_mac(struct eth_device *dev, char *s)
 	}
 
 	for (i = 0; i < 3; i++)
-		write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i);
+		write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
 
 	return 0;
 }
@@ -147,34 +154,30 @@ int eeprom(int argc, char *argv[])
 	int i, len, ret;
 	unsigned char buf[58], *p;
 
-	struct eth_device dev = {
-		.iobase = CONFIG_SMC91111_BASE
-	};
-
 	app_startup(argv);
-	if (get_version() != XF_VERSION) {
-		printf("Wrong XF_VERSION.\n");
-		printf("Application expects ABI version %d\n", XF_VERSION);
-		printf("Actual U-Boot ABI version %d\n", (int)get_version());
+	i = get_version();
+	if (i != XF_VERSION) {
+		printf("Using ABI version %d, but U-Boot provides %d\n",
+			XF_VERSION, i);
 		return 1;
 	}
 
-	if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
-		printf("SMSC91111 not found.\n");
+	if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
+		puts("SMSC91111 not found\n");
 		return 2;
 	}
 
 	/* Called without parameters - print MAC address */
 	if (argc < 2) {
-		verify_macaddr(&dev, NULL);
+		verify_macaddr(NULL);
 		return 0;
 	}
 
 	/* Print help message */
 	if (argv[1][1] == 'h') {
-		printf("VoiceBlue EEPROM writer\n");
-		printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
-		printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
+		puts("VoiceBlue EEPROM writer\n"
+			"Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n"
+			"Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
 		return 0;
 	}
 
@@ -191,7 +194,7 @@ int eeprom(int argc, char *argv[])
 			printf("Element %d: odd character count\n", i - 1);
 			return 3;
 		case -3:
-			printf("Out of EEPROM memory\n");
+			puts("Out of EEPROM memory\n");
 			return 3;
 		default:
 			p += ret;
@@ -200,16 +203,16 @@ int eeprom(int argc, char *argv[])
 	}
 
 	/* First argument (MAC) is mandatory */
-	set_mac(&dev, argv[1]);
-	if (verify_macaddr(&dev, argv[1])) {
-		printf("*** MAC address does not match! ***\n");
+	set_mac(argv[1]);
+	if (verify_macaddr(argv[1])) {
+		puts("*** HWaddr does not match! ***\n");
 		return 4;
 	}
 
 	while (len--)
 		*p++ = 0;
 
-	write_data(&dev, (u16 *)buf, sizeof(buf) >> 1);
+	write_data((u16 *)buf, sizeof(buf) >> 1);
 
 	return 0;
 }
diff --git a/board/voiceblue/eeprom_start.S b/board/voiceblue/eeprom_start.S
deleted file mode 100644
index 8f88de5c3b5..00000000000
--- a/board/voiceblue/eeprom_start.S
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2005  2N Telekomunikace
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- */
-
-.globl	_start
-_start:	b	eeprom