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authorTom Rini <trini@konsulko.com>2025-07-31 08:45:50 -0600
committerTom Rini <trini@konsulko.com>2025-07-31 10:04:32 -0600
commitf5e968a28e7cdc2c4365f5a382e02f074ee03fac (patch)
tree2f988c7102a977da562c28075e94e875ab5bcb94 /board
parenteef444c38994aee9cd3c6e4df5791b5f7209c8d8 (diff)
parente064db5fe77caaddb21a7793f266119ad89dd79a (diff)
Merge tag 'u-boot-stm32-20250731' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27236 - Add support for STM32 TIMERS and STM32 PWM on STM32MP25 - Add STM32MP13xx SPL and OpTee-OS start support - Fix header misuse in stm32 reset drivers - Fix STMicroelectronics spelling - Fix clk-stm32h7 wrong macros used in register read - Fix PRE_CON_BUF_ADDR on STM32MP13 - Fix clock identifier passed to struct scmi_clk_parent_set_in - Fix stm32 reset for STM32F4/F7 and H7 - Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig - Add STM32MP23 SoC and stm32mp235f-dk board support
Diffstat (limited to 'board')
-rw-r--r--board/st/common/Kconfig2
-rw-r--r--board/st/common/stpmic1.c51
-rw-r--r--board/st/stm32mp1/debug_uart.c21
-rw-r--r--board/st/stm32mp2/Kconfig14
4 files changed, 67 insertions, 21 deletions
diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig
index 5efac658cf4..94ec806949b 100644
--- a/board/st/common/Kconfig
+++ b/board/st/common/Kconfig
@@ -1,7 +1,7 @@
config CMD_STBOARD
bool "stboard - command for OTP board information"
depends on ARCH_STM32MP
- default y if TARGET_ST_STM32MP25X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP13X
+ default y if TARGET_ST_STM32MP13X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP23X || TARGET_ST_STM32MP25X
help
This compile the stboard command to
read and write the board in the OTP.
diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
index 45c2bb5bcea..b46f89dacb9 100644
--- a/board/st/common/stpmic1.c
+++ b/board/st/common/stpmic1.c
@@ -14,8 +14,19 @@
#include <power/pmic.h>
#include <power/stpmic1.h>
+static bool is_stm32mp13xx(void)
+{
+ if (!IS_ENABLED(CONFIG_STM32MP13X))
+ return false;
+
+ return of_machine_is_compatible("st,stm32mp131") ||
+ of_machine_is_compatible("st,stm32mp133") ||
+ of_machine_is_compatible("st,stm32mp135");
+}
+
int board_ddr_power_init(enum ddr_type ddr_type)
{
+ bool is_mp13 = is_stm32mp13xx();
struct udevice *dev;
bool buck3_at_1800000v = false;
int ret;
@@ -30,18 +41,21 @@ int board_ddr_power_init(enum ddr_type ddr_type)
switch (ddr_type) {
case STM32MP_DDR3:
/* VTT = Set LDO3 to sync mode */
- ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
- if (ret < 0)
- return ret;
-
- ret &= ~STPMIC1_LDO3_MODE;
- ret &= ~STPMIC1_LDO12356_VOUT_MASK;
- ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
-
- ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
- ret);
- if (ret < 0)
- return ret;
+ if (!is_mp13) {
+ /* Enable VTT only on STM32MP15xx */
+ ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+ if (ret < 0)
+ return ret;
+
+ ret &= ~STPMIC1_LDO3_MODE;
+ ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+ ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
+
+ ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ ret);
+ if (ret < 0)
+ return ret;
+ }
/* VDD_DDR = Set BUCK2 to 1.35V */
ret = pmic_clrsetbits(dev,
@@ -69,11 +83,14 @@ int board_ddr_power_init(enum ddr_type ddr_type)
mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
/* Enable VTT = LDO3 */
- ret = pmic_clrsetbits(dev,
- STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
- STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
- if (ret < 0)
- return ret;
+ if (!is_mp13) {
+ /* Enable VTT only on STM32MP15xx */
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+ if (ret < 0)
+ return ret;
+ }
mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
diff --git a/board/st/stm32mp1/debug_uart.c b/board/st/stm32mp1/debug_uart.c
index 24e3f9f2201..4c2149e0480 100644
--- a/board/st/stm32mp1/debug_uart.c
+++ b/board/st/stm32mp1/debug_uart.c
@@ -9,17 +9,32 @@
#include <asm/arch/stm32.h>
#include <linux/bitops.h>
+#if IS_ENABLED(CONFIG_STM32MP13X)
+#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0700)
+#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0768)
+#elif IS_ENABLED(CONFIG_STM32MP15X)
#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
+#endif
+#define GPIOA_BASE 0x50002000
#define GPIOG_BASE 0x50008000
void board_debug_uart_init(void)
{
- if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) {
- /* UART4 clock enable */
- setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
+ if (CONFIG_DEBUG_UART_BASE != STM32_UART4_BASE)
+ return;
+ /* UART4 clock enable */
+ setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
+
+ if (IS_ENABLED(CONFIG_STM32MP13X)) {
+ /* GPIOA clock enable */
+ writel(BIT(0), RCC_MP_AHB4ENSETR);
+ /* GPIO configuration for DH boards: Uart4 TX = A9 */
+ writel(0xfffbffff, GPIOA_BASE + 0x00);
+ writel(0x00000080, GPIOA_BASE + 0x24);
+ } else if (IS_ENABLED(CONFIG_STM32MP15X)) {
/* GPIOG clock enable */
writel(BIT(6), RCC_MP_AHB4ENSETR);
/* GPIO configuration for ST boards: Uart4 TX = G11 */
diff --git a/board/st/stm32mp2/Kconfig b/board/st/stm32mp2/Kconfig
index f91e25f1f9a..e88c71a278e 100644
--- a/board/st/stm32mp2/Kconfig
+++ b/board/st/stm32mp2/Kconfig
@@ -1,3 +1,17 @@
+if TARGET_ST_STM32MP23X
+
+config SYS_BOARD
+ default "stm32mp2"
+
+config SYS_VENDOR
+ default "st"
+
+config SYS_CONFIG_NAME
+ default "stm32mp23_st_common"
+
+source "board/st/common/Kconfig"
+endif
+
if TARGET_ST_STM32MP25X
config SYS_BOARD