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| author | Tom Rini <trini@konsulko.com> | 2025-05-21 08:59:10 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-05-21 09:00:21 -0600 |
| commit | 8f85a7345ed5df70a155f0630da72970eb01d87a (patch) | |
| tree | 10acf511e4f955f5874d9e64331c841609b4804a /boot/image.c | |
| parent | 0a87352281ade2b822ce0360e1f105f6e43a96e1 (diff) | |
| parent | ff6e20c32ff33c6963f7d0a79a0914681461f4fa (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26259
- Initial SPL support for T-Head TH1520 SoC
- Improve usability of TH1520 with mainline SPL
- Support building RV32 & RV64 images
- riscv: Improve jh7110 support
Diffstat (limited to 'boot/image.c')
| -rw-r--r-- | boot/image.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/boot/image.c b/boot/image.c index 139c5bd035a..45299a7dc33 100644 --- a/boot/image.c +++ b/boot/image.c @@ -92,7 +92,8 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_ARC, "arc", "ARC", }, { IH_ARCH_X86_64, "x86_64", "AMD x86_64", }, { IH_ARCH_XTENSA, "xtensa", "Xtensa", }, - { IH_ARCH_RISCV, "riscv", "RISC-V", }, + { IH_ARCH_RISCV, "riscv", "RISC-V 32 Bit",}, + { IH_ARCH_RISCV64, "riscv64", "RISC-V 64 Bit",}, { -1, "", "", }, }; |