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| author | Padmarao Begari <padmarao.begari@amd.com> | 2025-01-06 15:21:20 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2025-02-05 16:22:55 +0100 |
| commit | 1621851495d341efb9c62c07a3d82feaa12cd03e (patch) | |
| tree | 9a2e56ae72f92441d4b72843dcc111ca3473d8c5 /cmd/fpga.c | |
| parent | a1319b5487522b1cdf981ae8bb02118fc53a801f (diff) | |
spi: cadence_qspi: Fix OSPI DDR mode alignment issue
If the least significant bit of the address is set to one when
using the DDR protocol for data transfer then the results are
indeterminate for few flash devices. To fix this the least
significant bit of the address is set to zero.
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250106095120.800753-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'cmd/fpga.c')
0 files changed, 0 insertions, 0 deletions