diff options
| author | Minkyu Kang <mk7.kang@samsung.com> | 2010-03-15 10:51:36 +0900 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2010-03-15 10:51:36 +0900 |
| commit | 995a4b1d83a08223c82c1e15778b02e85e5bba51 (patch) | |
| tree | 0acb85278216df76d8fb7284b32d6dd95a1fc978 /cpu/arm_cortexa8/omap3/clock.c | |
| parent | a8d25fc26f681a9c4dfb062ebb4b00b9509a7966 (diff) | |
| parent | 44de3e8ff7ed48bf96ec6c5e2173187d9c1c61e6 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
board/davinci/da830evm/da830evm.c
board/edb93xx/sdram_cfg.c
board/esd/otc570/otc570.c
board/netstar/eeprom.c
board/netstar/eeprom_start.S
cpu/arm920t/ep93xx/timer.c
include/configs/netstar.h
include/configs/otc570.h
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'cpu/arm_cortexa8/omap3/clock.c')
| -rw-r--r-- | cpu/arm_cortexa8/omap3/clock.c | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c index 174c4531143..6330c9e5da4 100644 --- a/cpu/arm_cortexa8/omap3/clock.c +++ b/cpu/arm_cortexa8/omap3/clock.c @@ -40,7 +40,7 @@ *****************************************************************************/ u32 get_osc_clk_speed(void) { - u32 start, cstart, cend, cdiff, val; + u32 start, cstart, cend, cdiff, cdiv, val; struct prcm *prcm_base = (struct prcm *)PRCM_BASE; struct prm *prm_base = (struct prm *)PRM_BASE; struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; @@ -48,9 +48,15 @@ u32 get_osc_clk_speed(void) val = readl(&prm_base->clksrc_ctrl); - /* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1; - writel(val, &prm_base->clksrc_ctrl); + if (val & SYSCLKDIV_2) + cdiv = 2; + else if (val & SYSCLKDIV_1) + cdiv = 1; + else + /* + * Should never reach here! (Assume divider as 1) + */ + cdiv = 1; /* enable timer2 */ val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1; @@ -61,6 +67,7 @@ u32 get_osc_clk_speed(void) /* Enable I and F Clocks for GPT1 */ val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC; writel(val, &prcm_base->iclken_wkup); + val = readl(&prcm_base->fclken_wkup) | EN_GPT1; writel(val, &prcm_base->fclken_wkup); @@ -83,6 +90,11 @@ u32 get_osc_clk_speed(void) cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ cdiff = cend - cstart; /* get elapsed ticks */ + if (cdiv == 2) + { + cdiff *= 2; + } + /* based on number of ticks assign speed */ if (cdiff > 19000) return S38_4M; |