diff options
| author | Scott Sweeny <scott.sweeny@timesys.com> | 2010-09-01 12:02:01 -0400 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-09-01 12:06:18 -0400 |
| commit | 3456a4958ec2ecb2b2e35b1f37039fb28274f182 (patch) | |
| tree | bf6aef6608c5410ad8b7e4f49dc2cc58aad22538 /cpu/mpc512x/serial.c | |
| parent | e1dce181db649aadcf5c83e9459ebf53dd038073 (diff) | |
Freescale board patch for MPC5125_TWR board
Diffstat (limited to 'cpu/mpc512x/serial.c')
| -rw-r--r-- | cpu/mpc512x/serial.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c index 7db87a80a1a..6c334fbe971 100644 --- a/cpu/mpc512x/serial.c +++ b/cpu/mpc512x/serial.c @@ -67,8 +67,10 @@ int serial_init(void) fifo_init (psc); +#ifndef ADS5125 /* set MR register to point to MR1 */ psc->command = PSC_SEL_MODE_REG_1; +#endif /* disable Tx/Rx */ psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE; @@ -79,15 +81,22 @@ int serial_init(void) /* switch to UART mode */ psc->sicr = 0; - /* mode register points to mr1 */ /* configure parity, bit length and so on in mode register 1*/ +#ifdef CONFIG_ADS5125 + psc->mr1 = PSC_MODE_8_BITS | PSC_MODE_PARNONE; + psc->mr2 = PSC_MODE_1_STOPBIT; + + /* calculate divisor for setting PSC CTUR and CTLR registers */ + div = gd->ips_clk/(16 * gd->baudrate); +#else + /* mode register points to mr1 */ psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; /* now, mode register points to mr2 */ psc->mode = PSC_MODE_1_STOPBIT; - - /* calculate dividor for setting PSC CTUR and CTLR registers */ + /* calculate divisor for setting PSC CTUR and CTLR registers */ baseclk = (gd->ips_clk + 8) / 16; div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; +#endif psc->ctur = (div >> 8) & 0xff; /* set baudrate */ |