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| author | Wolfgang Denk <wd@denx.de> | 2009-04-01 22:43:51 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-04-01 22:43:51 +0200 |
| commit | da72af8d727e74093e5fcb3e8599eb8d0df7a749 (patch) | |
| tree | 8937781ff72c3841e2352863e3060f0b1a1808ed /cpu/mpc85xx/ddr-gen3.c | |
| parent | c2eb8be7f760a2efe30a495bfb10857838dcf3fa (diff) | |
| parent | fc39c2fd51e64707de4d61ed49479ebea2847e1b (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'cpu/mpc85xx/ddr-gen3.c')
| -rw-r--r-- | cpu/mpc85xx/ddr-gen3.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index 99c325a4ff1..8ac3d5fbebf 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -98,10 +98,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #endif /* - * 200 painful micro-seconds must elapse between + * 500 painful micro-seconds must elapse between * the DDR clock setup and the DDR config enable. + * DDR2 need 200 us, and DDR3 need 500 us from spec, + * we choose the max, that is 500 us for all of case. */ - udelay(200); + udelay(500); asm volatile("sync;isync"); /* Let the controller go */ |