diff options
| author | Peter Pearse <peter.pearse@arm.com> | 2008-01-07 15:34:22 +0000 |
|---|---|---|
| committer | Peter Pearse <peter.pearse@arm.com> | 2008-01-07 15:34:22 +0000 |
| commit | 4985ca5af3767ffe13ea96e1dc26f88c81084414 (patch) | |
| tree | 94db0464d5c7c643816dd3b4e823343496c2ed96 /cpu/mpc86xx/spd_sdram.c | |
| parent | 2ae64f5135e51bb18753884d1265b99e89b5aedd (diff) | |
| parent | 5c740711f0ea5b51414b341b71597c4a0751be74 (diff) | |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'cpu/mpc86xx/spd_sdram.c')
| -rw-r--r-- | cpu/mpc86xx/spd_sdram.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 059097f5142..265e033fb3d 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -1114,8 +1114,10 @@ spd_sdram(void) int memsize_ddr1 = 0; unsigned int law_size_ddr1; volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; +#ifdef CONFIG_DDR_INTERLEAVE + volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; +#endif #if (CONFIG_NUM_DDR_CONTROLLERS > 1) int memsize_ddr2_dimm1 = 0; @@ -1270,10 +1272,12 @@ spd_sdram(void) debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8); debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8); } + + debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2); + #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ - debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n", - memsize_ddr1, memsize_ddr2); + debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1); /* * If neither DDR controller is enabled return 0. |