diff options
| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-07-13 22:12:58 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-07-13 22:12:58 +0200 |
| commit | cf8f60f0eaeba44190fc9a0b56f0a53850ccb8c9 (patch) | |
| tree | 9ad4aaaef72a926b5e9dd588bf5d4074b74fc641 /cpu/mpc8xx/speed.c | |
| parent | d22d102808ddae3d40360df8d94e7f4239c88093 (diff) | |
| parent | 090eb73510838c0e8c20d80eea0d7f9e774ff6b5 (diff) | |
Merge with /home/mk/11-cmb1920/u-boot
Diffstat (limited to 'cpu/mpc8xx/speed.c')
| -rw-r--r-- | cpu/mpc8xx/speed.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 57f91c0aa04..101d5f9cb35 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -259,7 +259,11 @@ int get_clocks_866 (void) */ sccr_reg = immr->im_clkrst.car_sccr; sccr_reg &= ~SCCR_EBDF11; +#if defined(CONFIG_TQM885D) + if (gd->cpu_clk <= 80000000) { +#else if (gd->cpu_clk <= 66000000) { +#endif sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ gd->bus_clk = gd->cpu_clk; } else { @@ -360,7 +364,8 @@ static long init_pll_866 (long clk) #endif /* CONFIG_8xx_CPUCLK_DEFAULT */ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ + && !defined(CONFIG_TQM885D) /* * Adjust sdram refresh rate to actual CPU clock * and set timebase source according to actual CPU clock @@ -384,6 +389,6 @@ int adjust_sdram_tbs_8xx (void) return (0); } -#endif /* CONFIG_TQM8xxL/M, !TQM866M */ +#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ /* ------------------------------------------------------------------------- */ |