diff options
| author | Stefan Roese <sr@denx.de> | 2008-09-08 10:35:49 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-09-08 10:35:49 +0200 |
| commit | c351575c226eaad85f12b0d346e762260b263531 (patch) | |
| tree | c2c1748a95c589278cbf048c191728fd5a9ea753 /cpu/mpc8xxx/ddr/ctrl_regs.c | |
| parent | ac53ee8318678190bf3c68da477a84a657d86fb0 (diff) | |
| parent | 302e52e0b1d4c7f994991709d0cb6c3ea612cdb5 (diff) | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'cpu/mpc8xxx/ddr/ctrl_regs.c')
| -rw-r--r-- | cpu/mpc8xxx/ddr/ctrl_regs.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index ca675512a29..e6c2a5ce7cf 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -520,7 +520,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, unsigned int wr; /* Write Recovery */ unsigned int dll_res; /* DLL Reset */ unsigned int mode; /* Normal=0 or Test=1 */ - unsigned int caslat; /* CAS# latency */ + unsigned int caslat = 0;/* CAS# latency */ /* BT: Burst Type (0=Sequential, 1=Interleaved) */ unsigned int bt; unsigned int bl; /* BL: Burst Length */ @@ -572,7 +572,9 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, 0x6, /* 2.5 clocks */ 0x3 /* 3.0 clocks */ }; - caslat = mode_caslat_table[cas_latency - 1]; + caslat = mode_caslat_table[cas_latency - 1]; + } else { + printf("Warning: unknown cas_latency %d\n", cas_latency); } #elif defined(CONFIG_FSL_DDR2) caslat = cas_latency; |