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| author | Tom Rini <trini@konsulko.com> | 2023-01-09 11:30:08 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-01-09 11:30:08 -0500 |
| commit | cebdfc22da6eb81793b616e855bc4d6d89c1c7a6 (patch) | |
| tree | 44eaafcbe4866712d361304882e7d56ca0ef1682 /doc/README.fsl-ddr | |
| parent | 62e2ad1ceafbfdf2c44d3dc1b6efc81e768a96b9 (diff) | |
| parent | fe33066d246462551f385f204690a11018336ac8 (diff) | |
Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'doc/README.fsl-ddr')
| -rw-r--r-- | doc/README.fsl-ddr | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index cec5d94df4a..f44bb2aa25d 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -56,8 +56,8 @@ Table of 2-way interleaving modes supported in cpu/8xxx/ddr/ The ways to configure the ddr interleaving mode ============================================== 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting - under "CONFIG_EXTRA_ENV_SETTINGS", like: - #define CONFIG_EXTRA_ENV_SETTINGS \ + under "CFG_EXTRA_ENV_SETTINGS", like: + #define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=bank" \ ...... @@ -137,7 +137,7 @@ Memory testing options for mpc85xx 2. Memory test can be done with Power-On-Self-Test function, activated at compile time. - In order to enable the POST memory test, CONFIG_POST needs to be + In order to enable the POST memory test, CFG_POST needs to be defined in board configuraiton header file. By default, POST memory test performs a fast test. A slow test can be enabled by changing the flag at compiling time. To test memory bigger than 2GB, 36BIT support is needed. |