diff options
| author | Tom Rini <trini@konsulko.com> | 2022-10-31 14:43:04 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-10-31 14:43:04 -0400 |
| commit | a90afc6730e6c67ad37f4c98a02891a93b4ff971 (patch) | |
| tree | 724c085433631e142a56c052d667139cba29b4a6 /doc/SPL/README.omap3 | |
| parent | 6f38d91158e7e4199753b79e0a25c1a65175aba4 (diff) | |
| parent | 77bec9e3d8bd2dc307447b92a3d5cefd693a62ad (diff) | |
Merge branch '2022-10-31-vbe-implement-the-full-firmware-flow'
To quote Simon:
This series provides an implementation of VBE from TPL through to U-Boot
proper, using VBE to load the relevant firmware stages. It buils a single
image.bin file containing all the phases:
TPL - initial phase, loads VPL using binman symbols
VPL - main firmware phase, loads SPL using VBE parameters
SPL - loads U-Boot proper using VBE parameters
U-Boot - final firmware phase, where OS booting is processed
This series does not include the OS-booting phase. That will be the
subject of a future series.
The implementation is entirely handled by sandbox. It should be possible
to enable this on a real board without much effort, but that is also the
subject of a future series.
Diffstat (limited to 'doc/SPL/README.omap3')
| -rw-r--r-- | doc/SPL/README.omap3 | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/doc/SPL/README.omap3 b/doc/SPL/README.omap3 index c77ca4300af..c0f4bab29b3 100644 --- a/doc/SPL/README.omap3 +++ b/doc/SPL/README.omap3 @@ -36,17 +36,17 @@ Option 1 (SPL only): 0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata 0x4020E000 - 0x4020FFFC: Area for the SPL stack. 0x80000000 - 0x8007FFFF: Area for the SPL BSS. -0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot +0x80100000: CONFIG_TEXT_BASE of U-Boot 0x80208000 - 0x80307FFF: malloc() pool available to SPL. Option 2 (SPL or X-Loader): 0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata 0x4020E000 - 0x4020FFFC: Area for the SPL stack. -0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot +0x80008000: CONFIG_TEXT_BASE of U-Boot 0x87000000 - 0x8707FFFF: Area for the SPL BSS. 0x87080000 - 0x870FFFFF: malloc() pool available to SPL. For the areas that reside within DDR1 they must not be used prior to s_init() -completing. Note that CONFIG_SYS_TEXT_BASE must be clear of the areas that SPL +completing. Note that CONFIG_TEXT_BASE must be clear of the areas that SPL uses while running. This is why we have two versions of the memory map that only vary in where the BSS and malloc pool reside. |