diff options
| author | Simon Glass <sjg@chromium.org> | 2022-10-20 18:22:39 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-10-31 11:01:31 -0400 |
| commit | 984639039f4cfe32ec2cc531d6ace05326ac49eb (patch) | |
| tree | 472bf7e47978335a73c5d6025d3b83b534f7192b /doc/board/google/chromebook_coral.rst | |
| parent | 6f38d91158e7e4199753b79e0a25c1a65175aba4 (diff) | |
Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().
Rename it to resolve this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'doc/board/google/chromebook_coral.rst')
| -rw-r--r-- | doc/board/google/chromebook_coral.rst | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst index 4b585678dcf..8edbf0429cd 100644 --- a/doc/board/google/chromebook_coral.rst +++ b/doc/board/google/chromebook_coral.rst @@ -250,7 +250,7 @@ boots. Be warned that SPL can take 30 seconds without this cache! This is a known issue with Intel SoCs with modern DRAM and apparently cannot be improved. The MRC caches are used to work around this. -Once SPL is finished it loads U-Boot into SDRAM at CONFIG_SYS_TEXT_BASE, which +Once SPL is finished it loads U-Boot into SDRAM at CONFIG_TEXT_BASE, which is normally 1110000. Note that CAR is still active. @@ -355,7 +355,7 @@ Partial memory map f0000 CONFIG_ROM_TABLE_ADDR 120000 BSS (defined in u-boot-spl.lds) 200000 FSP-S (which is run after U-Boot is relocated) - 1110000 CONFIG_SYS_TEXT_BASE + 1110000 CONFIG_TEXT_BASE Speeding up SPL for development |