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| author | Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> | 2025-09-24 00:49:11 -0700 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-09-30 14:45:37 +0800 |
| commit | da57acb4c396cfc978c0652fec9dfb17a4f67ad8 (patch) | |
| tree | b7ab218286786f6f97078e0f3dfa533e1b151d45 /doc/develop | |
| parent | 060ed1bbbe0fd1a8583d09d7766cf3f194b23edc (diff) | |
arch: arm: socfpga: Configure USB3 System Manager registers
For successful reset staggering pulse operation, reset pulse
override bit is set. Port overcurrent bit 1, which in reality
reflects PIPE power present signal is set to avoid giving
false information of Vbus status to HPS controller.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'doc/develop')
0 files changed, 0 insertions, 0 deletions