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authorCaleb Connolly <caleb.connolly@linaro.org>2023-11-07 12:41:04 +0000
committerCaleb Connolly <caleb.connolly@linaro.org>2024-01-16 12:26:24 +0000
commit6acc44319bba5e4f5bcdacaa6412d617815472ed (patch)
tree4874c74b6becbc28e8f226702993b05518c269dc /doc/sphinx/kerneldoc.py
parent37ea1343ac92e614d40279273e35920a4827c310 (diff)
clk/qcom: add mnd_width to clk_rcg_set_rate_mnd()
This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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