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| author | Tom Rini <trini@konsulko.com> | 2022-10-31 14:43:04 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-10-31 14:43:04 -0400 |
| commit | a90afc6730e6c67ad37f4c98a02891a93b4ff971 (patch) | |
| tree | 724c085433631e142a56c052d667139cba29b4a6 /doc/uImage.FIT/source_file_format.txt | |
| parent | 6f38d91158e7e4199753b79e0a25c1a65175aba4 (diff) | |
| parent | 77bec9e3d8bd2dc307447b92a3d5cefd693a62ad (diff) | |
Merge branch '2022-10-31-vbe-implement-the-full-firmware-flow'
To quote Simon:
This series provides an implementation of VBE from TPL through to U-Boot
proper, using VBE to load the relevant firmware stages. It buils a single
image.bin file containing all the phases:
TPL - initial phase, loads VPL using binman symbols
VPL - main firmware phase, loads SPL using VBE parameters
SPL - loads U-Boot proper using VBE parameters
U-Boot - final firmware phase, where OS booting is processed
This series does not include the OS-booting phase. That will be the
subject of a future series.
The implementation is entirely handled by sandbox. It should be possible
to enable this on a real board without much effort, but that is also the
subject of a future series.
Diffstat (limited to 'doc/uImage.FIT/source_file_format.txt')
| -rw-r--r-- | doc/uImage.FIT/source_file_format.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 0a03c942bda..4640e38e3cc 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -190,6 +190,9 @@ the '/images' node should have the following layout: Xilinx Zynq UltraScale+ (ZymqMP) device. "u-boot,zynqmp-fpga-enc" - encrypted FPGA bitstream for Xilinx Zynq UltraScale+ (ZynqMP) device. + - phase : U-Boot phase for which the image is intended. + "spl" - image is an SPL image + "u-boot" - image is a U-Boot image Optional nodes: - hash-1 : Each hash sub-node represents separate hash or checksum |