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| author | Cem Tenruh <c.tenruh@phytec.de> | 2023-06-16 10:28:13 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2023-07-13 11:29:40 +0200 |
| commit | 7a478c836a243d1682b50dd82576432fc6e11825 (patch) | |
| tree | ade78ba2e589cc3da3161b86c8c4e710f8700aea /drivers/adc/stm32-adc-core.h | |
| parent | ff1dd520243320259b654065821b0f5cdea9f551 (diff) | |
board: phytec: phycore_imx8mm: Update lpddr4_timing
Update RAM Timings for 2GB RAM based on DDR Controller Configuration
Spreadsheet revision 22. Including the update of the refresh
rate to workaround errata ERR050805.
Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
Diffstat (limited to 'drivers/adc/stm32-adc-core.h')
0 files changed, 0 insertions, 0 deletions