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| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2023-02-06 16:10:47 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-02-17 19:07:48 +0800 |
| commit | d8a146d19b9a39a9b90aa40c8e61c5d0ddfa17e5 (patch) | |
| tree | 57185976e0b05d9ccfe860e7602a6f94275343ed /drivers/cache/cache-v5l2.c | |
| parent | 51415fa634d2ff0e2d10eeefb739cdb941d19412 (diff) | |
riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.
[0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'drivers/cache/cache-v5l2.c')
0 files changed, 0 insertions, 0 deletions