diff options
| author | Tom Rini <trini@konsulko.com> | 2022-05-10 15:28:02 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-05-10 15:28:02 -0400 |
| commit | 21e25992c86306b41caafcf85efc47d66f5efa6e (patch) | |
| tree | 3c9f1ccb01f1a83f077064b4e4f4e028760f2e39 /drivers/clk/clk_stm32mp1.c | |
| parent | b4eb57766314062e3dd1ee8e439d2cb2d5dc33d8 (diff) | |
| parent | e198d4fe7c34cbb97d7d3cbf31d3a78a5ecc43f7 (diff) | |
Merge tag 'u-boot-stm32-20220510' of https://source.denx.de/u-boot/custodians/u-boot-stm
Add new STM32 MCU boards and Documentation
STM32 programmer improvements
video: support several LTDC HW versions and fix data enable polarity
board: fix stboard error message, consider USB cable connected when boot device is USB
configs: stm32mp1: set console variable for extlinux.conf
configs: stm32mp1: add support for baudrate higher than 115200 for ST-Link
ARM: stm32mp: Fix Silicon version handling and ft_system_setup()
phy: stm32-usbphyc: Add DT phy tuning support
arm: dts: stm32mp15: alignment with v5.18
ram: Conditionally enable ASR
mach-stm32mp: psci: retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
configs: Use TFTP_TSIZE on DHSOM and STMicroelectronics boards
ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
pinctrl: stm32: rework GPIO holes management
Diffstat (limited to 'drivers/clk/clk_stm32mp1.c')
| -rw-r--r-- | drivers/clk/clk_stm32mp1.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 83ab6b728ed..452550066e2 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -2205,7 +2205,7 @@ static void stm32mp1_osc_init(struct udevice *dev) for (i = 0; i < NB_OSC; i++) { if (clk_get_by_name(dev, name[i], &priv->osc_clk[i])) - dev_dbg(dev, "No source clock \"%s\"", name[i]); + dev_dbg(dev, "No source clock \"%s\"\n", name[i]); else dev_dbg(dev, "%s clock rate: %luHz\n", name[i], clk_get_rate(&priv->osc_clk[i])); |