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authorTom Rini <trini@konsulko.com>2022-09-26 11:28:14 -0400
committerTom Rini <trini@konsulko.com>2022-09-26 11:28:14 -0400
commit55ccdee3155c6cc30eeee846879d06aba6e3fabe (patch)
tree4cda01be7fa0553410ffc193f4f931910efbbf57 /drivers/clk/clk_versal.c
parentffa2c88bcf8618b6d6fb71f5263beede9a179b20 (diff)
parentf2641f066b53a2bbb933bccffd696a875fd9adf5 (diff)
Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.01-rc1 (round 2) xilinx: - Add support for new Versal NET SOC zynqmp: - Use mdio bus for ethernet phy description - Wire ethernet phy reset via i2c-gpio versal: - Config cleanup
Diffstat (limited to 'drivers/clk/clk_versal.c')
-rw-r--r--drivers/clk/clk_versal.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index a9dd57b098f..b2f62061cea 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -739,6 +739,7 @@ static struct clk_ops versal_clk_ops = {
static const struct udevice_id versal_clk_ids[] = {
{ .compatible = "xlnx,versal-clk" },
+ { .compatible = "xlnx,versal-net-clk" },
{ }
};