diff options
| author | Tom Rini <trini@konsulko.com> | 2020-03-02 09:20:12 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-03-02 09:20:12 -0500 |
| commit | bd7bb38699412bf95449bf9f23aa625c0436eae6 (patch) | |
| tree | 4e30bec98504a3923d40df2594b48c173032e192 /drivers/clk/clk_versal.c | |
| parent | 5045289820835ce0baf5d7cea86f9fdc6170d189 (diff) | |
| parent | 25974079750c5fbf920a226a26d8cb9b1aff2544 (diff) | |
Merge tag 'xilinx-for-v2020.04-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx fixes for v2020.04-rc4
- Fix link good bit handling in dp83867
- Rename generic Zynq defconfig
- Fix zybo z7 low leve setup
- Fix error path in zynq_gem driver and fix 64bit usage
- Fix invalid clock name quieries for Versal
- Fix zynq/zynqmp SPL low level configuration via DT selection
Diffstat (limited to 'drivers/clk/clk_versal.c')
| -rw-r--r-- | drivers/clk/clk_versal.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 9d4d2149e32..d3673a5c8b8 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -571,6 +571,12 @@ static void versal_get_clock_info(void) continue; clock[i].valid = attr & CLK_VALID_MASK; + + /* skip query for Invalid clock */ + ret = versal_is_valid_clock(i); + if (ret != CLK_VALID_MASK) + continue; + clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ? CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT; nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK; |