diff options
| author | Christian Marangi <ansuelsmth@gmail.com> | 2024-08-02 15:53:13 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-08-19 16:13:13 -0600 |
| commit | 2d20cc40640c7eaa4e93fe7949326487c9c76077 (patch) | |
| tree | bb3934d26cc0e4b1997f83cda82a946a1709daaa /drivers/clk/mediatek | |
| parent | 2967f2118216eed2b9120b3995f13bfcf0d4aaf5 (diff) | |
clk: mediatek: mt7981: fix support for pwm3 clock
Add and fix support for pwm3 clock. In the pwm DTSI node we were
actually using PWM2 clock for PWM3. Now that we have correct ID also add
the missing entry of gate and mux to support PWM3 clock.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Diffstat (limited to 'drivers/clk/mediatek')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7981.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 4435430dcde..7b692186dc1 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -381,6 +381,8 @@ static const struct mtk_composite infra_muxes[] = { 9, 1), INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10, 11, 1), + INFRA_MUX(CK_INFRA_PWM3_SEL, "infra_pwm3_sel", infra_pwm1_parents, 0x10, + 15, 1), INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, 0x10, 13, 2), INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, @@ -445,6 +447,7 @@ static const struct mtk_gate infracfg_ao_gates[] = { GATE_INFRA0_INFRA(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BSEL, 2), GATE_INFRA0_INFRA(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM1_SEL, 3), GATE_INFRA0_INFRA(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM2_SEL, 4), + GATE_INFRA0_INFRA(CK_INFRA_PWM3_CK, "infra_pwm3", CK_INFRA_PWM3_SEL, 27), GATE_INFRA0_TOP(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_TOP_SYSAXI, 6), GATE_INFRA0_TOP(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_TOP_SYSAXI, 8), GATE_INFRA0_TOP(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_TOP_F26M_SEL, 9), |