clk: microchip: mpfs: support new syscon based devicetree configuration

Why get a devicetree description wrong once when you can get it wrong
twice? The original mistake, which the driver supports was failing to
describe the main PLL that the "cfg" and "periph" clocks parented by.
The second mistake was describing the "cfg" and "periph" clocks a
reg region within the clock controller, rather as two registers within
a syscon region that also contains pinctrl, interrupt muxing controls
and other functions.

Make up for lost time and describe these regions as they should have
been originally, preserving support for the existing two configurations
for the sake of existing systems with firmware-provided devicetrees.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

1 files changed, 50 insertions, 13 deletions

diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
index 0a82777ff74..2c6694f0035 100644
--- a/drivers/clk/microchip/mpfs_clk.c
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -9,25 +9,39 @@
 #include <log.h>
 #include <dm/device.h>
 #include <dm/devres.h>
+#include <dm/ofnode.h>
 #include <dm/uclass.h>
+#include <regmap.h>
+#include <syscon.h>
 #include <dt-bindings/clock/microchip-mpfs-clock.h>
 #include <linux/err.h>
 
 #include "mpfs_clk.h"
 
-static int mpfs_clk_probe(struct udevice *dev)
+static int mpfs_clk_syscon_probe(struct udevice *dev, void __iomem **msspll_base,
+				 struct regmap **regmap)
 {
-	struct clk *parent_clk = dev_get_priv(dev);
-	struct clk clk_msspll = { .id = CLK_MSSPLL };
-	void __iomem *base;
-	void __iomem *msspll_base;
-	int ret;
+	ofnode node;
 
-	base = dev_read_addr_index_ptr(dev, 0);
-	if (!base)
-		return -EINVAL;
+	node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-mss-top-sysreg");
+	if (!ofnode_valid(node))
+		return -ENODEV;
 
-	ret = clk_get_by_index(dev, 0, parent_clk);
+	*regmap = syscon_node_to_regmap(node);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	*msspll_base = dev_read_addr_index_ptr(dev, 0);
+
+	return 0;
+}
+
+static int mpfs_clk_old_format_probe(struct udevice *dev, void __iomem **msspll_base,
+				     struct regmap **regmap)
+{
+	int ret;
+
+	ret = regmap_init_mem_index(dev_ofnode(dev), regmap, 0);
 	if (ret)
 		return ret;
 
@@ -40,7 +54,30 @@ static int mpfs_clk_probe(struct udevice *dev)
 	 * Otherwise, skip registering it & pass the reference clock directly
 	 * to the cfg clock registration function.
 	 */
-	msspll_base = dev_read_addr_index_ptr(dev, 1);
+	*msspll_base = dev_read_addr_index_ptr(dev, 1);
+
+	return 0;
+}
+
+static int mpfs_clk_probe(struct udevice *dev)
+{
+	struct clk *parent_clk = dev_get_priv(dev);
+	struct clk clk_msspll = { .id = CLK_MSSPLL };
+	struct regmap *regmap;
+	void __iomem *msspll_base;
+	int ret;
+
+	ret = clk_get_by_index(dev, 0, parent_clk);
+	if (ret)
+		return ret;
+
+	ret = mpfs_clk_syscon_probe(dev, &msspll_base, &regmap);
+	if (ret) {
+		ret = mpfs_clk_old_format_probe(dev, &msspll_base, &regmap);
+		if (ret)
+			return ret;
+	}
+
 	if (msspll_base) {
 		ret = mpfs_clk_register_msspll(msspll_base, parent_clk);
 		if (ret)
@@ -50,11 +87,11 @@ static int mpfs_clk_probe(struct udevice *dev)
 		parent_clk = &clk_msspll;
 	}
 
-	ret = mpfs_clk_register_cfgs(base, parent_clk);
+	ret = mpfs_clk_register_cfgs(parent_clk, regmap);
 	if (ret)
 		return ret;
 
-	ret = mpfs_clk_register_periphs(base, dev);
+	ret = mpfs_clk_register_periphs(dev, regmap);
 
 	return ret;
 }