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| author | Yao Zi <ziyao@disroot.org> | 2025-05-30 09:48:48 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2025-06-09 10:44:06 +0800 |
| commit | 85cfabe895f4f32a5b65c114ebef7793321d5e01 (patch) | |
| tree | 89c18fa8563ab8076b047a1d81300dc812d613b5 /drivers/clk/stm32/clk-stm32-core.c | |
| parent | 0463545678883b8d2b417eea08c76d47396104b7 (diff) | |
riscv: cpu: th1520: Support cache enabling/disabling in M mode only
These operations rely on a customized M-mode CSR, MHCR, which isn't
available when running in S mode.
Let's fallback to the generic weak stub when running in S mode to avoid
illegal accesses.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'drivers/clk/stm32/clk-stm32-core.c')
0 files changed, 0 insertions, 0 deletions