diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2019-01-29 15:54:09 +0000 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-01-29 23:30:11 +0530 |
| commit | bb3e5aa2896d69a6fe86861004d7d4e33824efbe (patch) | |
| tree | 8f38de7357c03681bc0309bd76ab52fe00e02e06 /drivers/clk/sunxi/clk_a31.c | |
| parent | 1659156c74fb575d851fc1f43818d232712e776b (diff) | |
sunxi: clk: add MMC gates/resets
Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.
We don't advertise the mod clock yet, as this is still handled by the
MMC driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: add V3S, A80 gates/resets]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'drivers/clk/sunxi/clk_a31.c')
| -rw-r--r-- | drivers/clk/sunxi/clk_a31.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index a38d76cb7c7..5bd8b7dcccf 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -13,6 +13,10 @@ #include <dt-bindings/reset/sun6i-a31-ccu.h> static struct ccu_clk_gate a31_gates[] = { + [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)), + [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)), + [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)), + [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)), [CLK_AHB1_OTG] = GATE(0x060, BIT(24)), [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)), [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)), @@ -40,6 +44,10 @@ static struct ccu_reset a31_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), + [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)), + [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)), + [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)), + [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)), [RST_AHB1_OTG] = RESET(0x2c0, BIT(24)), [RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)), [RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)), |