diff options
| author | Ye Li <ye.li@nxp.com> | 2021-03-25 17:30:36 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-04-08 20:29:53 +0200 |
| commit | 2ff17d2f74c544111478437971a7dd15d3468c02 (patch) | |
| tree | e3a75c0355e54cfd1f576c1bc8ad7abdaab6cc3e /drivers/crypto/fsl/fsl_hash.c | |
| parent | 58fc03e2a65884c17841dd4eee58c97bbeb2297b (diff) | |
crypto: fsl: refactor for 32 bit version CAAM support on ARM64
Previous patch "MLK-18044-4: crypto: caam: Fix pointer size to 32bit
for i.MX8M" breaks the 64 bits CAAM.
Since i.MX CAAM are all 32 bits no matter the ARM arch (32 or 64),
to adapt and not break 64 bits CAAM support, add a new config
CONFIG_CAAM_64BIT and new relevant type "caam_dma_addr_t".
This config is default enabled when CONFIG_PHYS_64BIT is set except
for iMX8M.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/crypto/fsl/fsl_hash.c')
| -rw-r--r-- | drivers/crypto/fsl/fsl_hash.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 75500a621fd..8b5c26db070 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP * */ @@ -88,7 +87,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf, enum caam_hash_algos caam_algo) { uint32_t final; - phys_addr_t addr = virt_to_phys((void *)buf); + caam_dma_addr_t addr = virt_to_phys((void *)buf); struct sha_ctx *ctx = hash_ctx; if (ctx->sg_num >= MAX_SG_32) { @@ -96,12 +95,12 @@ static int caam_hash_update(void *hash_ctx, const void *buf, return -EINVAL; } -#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) +#ifdef CONFIG_CAAM_64BIT sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32)); #else sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0); #endif - sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (uint32_t)addr); + sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (caam_dma_addr_t)addr); sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag, (size & SG_ENTRY_LENGTH_MASK)); |