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authorGreentime Hu <greentime.hu@sifive.com>2022-01-20 16:41:28 +0800
committerMichal Simek <michal.simek@xilinx.com>2022-02-01 17:11:33 +0100
commit19fdc166f78a68bec60ca13b0c71a739fb4d0a73 (patch)
treed7b075728c7c452c14dc7f5d8ebf7a4597531026 /drivers/ddr/altera/sdram_agilex.c
parente6e3b9d7b55ce2563f9da0b5991605f15bd38163 (diff)
net: xilinx: fix the wrong dma base address issue
If we just use fdtdec_get_addr_size_fixed to get "reg" it will use 64bit address cell to get the base address. soc { #address-cells = <1>; #size-cells = <1>; compatible ="SiFive,FU500-soc", "fu500-soc", "sifive-soc", "simple-bus"; ranges; L28: axidma@30010000 { #dma-cells = <1>; compatible = "xlnx,axi-dma-1.00.a"; axistream-connected = <&L27>; axistream-control-connected = <&L27>; clocks = <&L1>; interrupt-parent = <&L6>; interrupts = <32 33>; reg = <0x30010000 0x4000>; fdtdec_get_addr_size_fixed: reg: addr=3001000000004000 We should get the base address through its parent's address-cells and size-cells settings. So we should use fdtdec_get_addr_size_auto_parent() to get correct base address. After applying this patch, we can get the correct base address of dma by replacing fdtdec_get_addr_size_fixed() with fdtdec_get_addr_size_auto_parent(). fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=30010000 Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Link: https://lore.kernel.org/r/20220120084128.1892101-1-andy.chiu@sifive.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex.c')
0 files changed, 0 insertions, 0 deletions