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| author | Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> | 2024-06-14 18:21:10 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2024-06-17 16:02:30 +0200 |
| commit | 37bd12551310e4c63a8d84bd05a98a83cf92105b (patch) | |
| tree | f96ef06ec4bf6930357e41ab809c9e76f51ccede /drivers/ddr/altera/sdram_agilex.c | |
| parent | 62a3e4016ab1938b1c2a2639eb772b31e98c25b6 (diff) | |
xilinx: versal-net: Add env redund offset
ENV_OFFSET_REDUND config is by default set to 0 for flashes.
Saving the env variables is overwriting data at 0 offset,
which is wrong. So add default redund env offset
ENV_OFFSET_REDUND at 0x7F00000 for Versal NET platform.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240614125110.23058-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex.c')
0 files changed, 0 insertions, 0 deletions