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authorWeijie Gao <weijie.gao@mediatek.com>2022-09-09 19:59:59 +0800
committerTom Rini <trini@konsulko.com>2022-09-23 15:09:16 -0400
commit7fb33e9aea514cfd873d8005954108a482e9e693 (patch)
treec940be0ad748c90af19c5c75772bc8eaf9d51c0e /drivers/ddr/altera/sdram_agilex.c
parent59acdf8afe4a5c676f8b6ed7af48821980a2bda5 (diff)
clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock
The mtk clock framework in u-boot uses array index for searching clock parent (kernel uses strings for search), so we need to specify a special clock with ID=0 for CLK_XTAL in u-boot. In the mt7622/mt7629 clock tree, the clocks with ID=0 never call mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we expected. However for newer chips, they may have some clocks with ID=0 not representing the xtal clock and still needs mtk_topckgen_get_mux_rate be called. Current logic will make entire clock driver not working. This patch adds a flag to indicate that whether a clock driver needs clocks with ID=0 to call mtk_topckgen_get_mux_rate. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex.c')
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