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| author | Michal Simek <michal.simek@amd.com> | 2024-05-29 16:47:59 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2024-06-17 16:02:29 +0200 |
| commit | 96cec1bbc9ed108de3fab582bd8ae26775c01e0b (patch) | |
| tree | 175ce65240ea1ce021e0fe3efb84373505ca1e3f /drivers/ddr/altera/sdram_agilex.c | |
| parent | 40f5046c221a7b2719c49b51acefe12914b213e5 (diff) | |
soc: versal2: Add SoC driver for AMD Versal Gen 2
Communication is happening via firmware interface (SMC) or via direct
register reading if firmware driver is not available.
Also enable it via defconfig.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/22cf9c765e47ab03dbf2b8363e6626e809113432.1716994063.git.michal.simek@amd.com
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex.c')
0 files changed, 0 insertions, 0 deletions