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| author | Heesub Shin <heesub@gmail.com> | 2024-04-28 23:24:03 +0900 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2024-06-18 08:55:52 +0200 |
| commit | 9ea73f6f53310c9eede926e039c9a281aa9f6447 (patch) | |
| tree | cfbb3a4808271aa30e13dbf1d28eacf88f93eee2 /drivers/ddr/altera/sdram_agilex.c | |
| parent | 2ae44edf1d341db1a0102150e02f463c90d657a0 (diff) | |
ARM: dts: stm32: use internal clock for Tx for stm32mp157c-odyssey
In Odyssey board, we should use the internal clock from RCC as the
transmit clock, instead of the external clock from ETH_CLK125 pad. This
commit adds a property, st,eth-clk-sel, so that the ETH_CLK_SEL mux
selects ETH_CLK.
Signed-off-by: Heesub Shin <heesub@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex.c')
0 files changed, 0 insertions, 0 deletions