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| author | Robert Marko <robert.marko@sartura.hr> | 2024-05-28 14:31:04 +0200 |
|---|---|---|
| committer | Caleb Connolly <caleb.connolly@linaro.org> | 2024-07-05 12:04:47 +0200 |
| commit | f3c4accc2f3443a8f79ea2011c5e378984f92b0a (patch) | |
| tree | e26f5b27320f739193a422d278a8ab6ed60d3e6e /drivers/ddr/altera/sdram_agilex.c | |
| parent | 308a4642ae757400a91a5dcefd746dc9b3c0402e (diff) | |
clock: qcom: ipq4019: add I2C clocks
I2C clocks are not initialized by the SBL, so lets add support for clocks
required by both of the QUP I2C controllers.
BLSP1 AHB clock is already initialized by SBL, but QUP I2C driver is
requesting it so we have to add it to the enable list.
Based off QCS404 clock driver.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex.c')
0 files changed, 0 insertions, 0 deletions