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| author | Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com> | 2025-02-18 16:35:03 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-02-25 10:54:00 -0600 |
| commit | 034ebe3302200c033078455c5774ed739cd4f2ac (patch) | |
| tree | b0d34788eccb7b693097ff5c4f25d04d42708b4a /drivers/ddr/altera/sdram_agilex5.c | |
| parent | 19f20cfc49e385dd5ae5583ae68bd31f20de622c (diff) | |
arm: socfpga: smc: Add memory coherency support to mailbox command
As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
perform cache flush of buffers that are shared between U-Boot and
ATF using secure monitor calls.
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex5.c')
0 files changed, 0 insertions, 0 deletions