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| author | Andre Przywara <andre.przywara@arm.com> | 2025-02-26 11:37:12 +0000 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2025-03-27 00:26:35 +0000 |
| commit | 720023c85f0c5e78893536e137994bcca1b70282 (patch) | |
| tree | 94a21481b36b60860518ace2f529297ad0a90140 /drivers/ddr/altera/sdram_agilex5.c | |
| parent | 46c291e14779d83cb216c9177cf7bb327005382b (diff) | |
sunxi: sun50i_h6: clock: fix PLL_PERIPH0 rate calculation
On the Allwinner D1/R528/T113-s3 SoCs (NCAT2) the factors encoded in
the PLL register describe the doubled clock rate, as in the other SoCs.
Correct for that by always dividing the calculated rate by 2, except on
the H6, where we need a divisor of 4 (no change here).
This corrects the PERIPH0 clock rate as read by the MMC driver, and
actually doubles the MMC performance on those NCAT2 chips.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex5.c')
0 files changed, 0 insertions, 0 deletions