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| author | Andre Przywara <andre.przywara@arm.com> | 2024-09-12 02:19:45 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2025-07-27 22:57:35 +0100 |
| commit | 869d396191ed226b66d9fe99e89230b359478d82 (patch) | |
| tree | 6139394c179f737940ec1f59ae4a4981e0e760c9 /drivers/ddr/altera/sdram_agilex5.c | |
| parent | 14c66b9e3510aa3a6c0f99ba1534c329e38dd94f (diff) | |
sunxi: mmc: add support for Allwinner A523 MMC mod clock
The Allwinner A523 SoC has a slightly changed mod clock, where the P
factor, formerly a shift value, is now a second divider value.
Also the input clock is not PLL_PERIPH0 (600MHz) anymore, but
PLL_PERIPH0_400M (for MMC0/1), so adjust the input rate calculation
accordingly. MMC2 has a different set of parents, so the input clock
is 800 MHz there.
Adjust for all of this.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex5.c')
0 files changed, 0 insertions, 0 deletions