diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2025-01-29 23:16:25 +0000 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2025-07-27 22:57:35 +0100 |
| commit | f02e64d011745de095b8072fd3b0b34f888144e6 (patch) | |
| tree | c66805b6dcaba6820ec06f71e878420d31141de9 /drivers/ddr/altera/sdram_s10.c | |
| parent | 4c3b5fcd810081bd7f3c51859fe1b5f0c159803c (diff) | |
sunxi: clock: H6: unify PLL control bit definitions
The Allwinner PLLs share most of their control bits, they differ mostly
in the factors and dividers.
Drop the PLL specific definition of those common bits, and use one
shared macro, for all PLLs.
This requires changing the users in the SPL clock and DRAM code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/ddr/altera/sdram_s10.c')
0 files changed, 0 insertions, 0 deletions