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| author | Tom Rini <trini@konsulko.com> | 2019-07-29 09:03:11 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-07-29 09:03:11 -0400 |
| commit | 92430b8fc8aac3b4ab92e9ca8a09d83c4788c609 (patch) | |
| tree | 741586740ac365252852d8dcdbbedf9e57d2b81d /drivers/ddr/altera/sequencer.h | |
| parent | ad4a699cfe36639979d27a1045d766397b2cb0bb (diff) | |
| parent | a89c2adc3d2834a7c79c1685155a8b8952cf77f4 (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga
- Various gen5 fixes
Diffstat (limited to 'drivers/ddr/altera/sequencer.h')
| -rw-r--r-- | drivers/ddr/altera/sequencer.h | 36 |
1 files changed, 29 insertions, 7 deletions
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index d7f6935201f..4a03c3fdf98 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -6,14 +6,16 @@ #ifndef _SEQUENCER_H_ #define _SEQUENCER_H_ -#define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \ - / rwcfg->mem_if_write_dqs_width) -#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \ - / rwcfg->mem_if_write_dqs_width) +#define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \ + / seq->rwcfg->mem_if_write_dqs_width) +#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \ + seq->rwcfg->true_mem_data_mask_width \ + / seq->rwcfg->mem_if_write_dqs_width) -#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \ - / rwcfg->mem_if_write_dqs_width) -#define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS) +#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (seq->rwcfg->mem_if_read_dqs_width \ + / seq->rwcfg->mem_if_write_dqs_width) +#define NUM_RANKS_PER_SHADOW_REG (seq->rwcfg->mem_number_of_ranks \ + / NUM_SHADOW_REGS) #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400 @@ -256,6 +258,26 @@ struct socfpga_sdr { u8 _align9[0xea4]; }; +struct socfpga_sdrseq { + const struct socfpga_sdram_rw_mgr_config *rwcfg; + const struct socfpga_sdram_io_config *iocfg; + const struct socfpga_sdram_misc_config *misccfg; + /* calibration steps requested by the rtl */ + u16 dyn_calib_steps; + /* + * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option + * instead of static, we use boolean logic to select between + * non-skip and skip values + * + * The mask is set to include all bits when not-skipping, but is + * zero when skipping + */ + + u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */ + struct gbl_type gbl; + struct param_type param; +}; + int sdram_calibration_full(struct socfpga_sdr *sdr); #endif /* _SEQUENCER_H_ */ |