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authorCaleb Connolly <caleb.connolly@linaro.org>2024-02-26 17:26:27 +0000
committerCaleb Connolly <caleb.connolly@linaro.org>2024-03-01 14:45:25 +0000
commitc6f4985a04f50dead54fee43745fca87107bace7 (patch)
tree680e8937099a8f799621f32d658c7ec8a749945d /drivers/ddr/altera
parent2bdc48f7fdcf412d9a67c07673bf7e7202628186 (diff)
mach-snapdragon: carve out no-map regions
On Qualcomm platforms, the TZ may already have certain memory regions under protection by the time U-Boot starts. There is a rare case on some platforms where the prefetcher might speculatively access one of these regions resulting in a board crash (TZ traps and then resets the board). We shouldn't be accessing these regions from within U-Boot anyway, so let's mark them all with PTE_TYPE_FAULT to prevent any speculative access and correctly trap in EL1 rather than EL3. Some lower level FDT functions are used here relying on some assumptions about how Qualcomm devicetrees are laid out (#address/size-cells being 2 for reserved-memory), as this is the only way to make this acceptably fast enough with dcache off. The full fat implementation takes 1800ms on SDM845, the implementation in this patch takes <1. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Diffstat (limited to 'drivers/ddr/altera')
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