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| author | Tom Rini <trini@konsulko.com> | 2025-07-31 08:42:06 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-07-31 08:42:06 -0600 |
| commit | eef444c38994aee9cd3c6e4df5791b5f7209c8d8 (patch) | |
| tree | cea1d9071449690a92258961ca876a42ca0bc739 /drivers/ddr/altera | |
| parent | 79f3e77133bd7248e4579827effc13f97a32a8a8 (diff) | |
| parent | 4064e7c9fc42c1c376bd919a80b451273472f3df (diff) | |
Merge tag 'u-boot-socfpga-next-20250731' of https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request includes updates for the SoCFPGA platform intended for the 2025.10 release
cycle. The highlights focus on enabling the Power Manager for Agilex5, NAND boot support
enhancements, and various bug fixes and cleanups across SoCFPGA components.
CI:
* https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27221
Summary of changes:
Agilex5 Power Manager:
* Initial driver support and DT bindings are added for the Agilex5 Power Manager, enabling
better power domain control.
NAND Boot Support for Agilex5:
* SPL support for NAND boot is enabled.
* UBI/UBIFS support is configured in defconfigs.
* Memory layout updates (malloc and BSS relocation) ensure proper boot behavior.
Code Quality Improvements:
* Coverity and runtime bug fixes (e.g., jtag_usercode check, sub-device conditionals).
* Several cleanup patches addressing formatting, logic, and initialization issues.
General Maintenance:
* SPDX license tags and header include fixes.
* Device tree updates to limit SPI clock frequency and other minor adjustments.
These contributions come from Alif Zakuan Yuslaimi, Andrew Goodbody, Dinesh Maniyam, Naresh
Kumar Ravulapalli, and Tingting Meng.
This patch set has been tested on Agilex 5 devkit.
Diffstat (limited to 'drivers/ddr/altera')
| -rw-r--r-- | drivers/ddr/altera/sdram_n5x.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index d1fc93b6bdd..17ec6afa82b 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -346,25 +346,25 @@ struct ddr_handoff { phys_addr_t cntlr_base; size_t cntlr_total_length; enum ddr_type cntlr_t; - size_t cntlr_handoff_length; + int cntlr_handoff_length; /* Second controller attributes*/ phys_addr_t cntlr2_handoff_base; phys_addr_t cntlr2_base; size_t cntlr2_total_length; enum ddr_type cntlr2_t; - size_t cntlr2_handoff_length; + int cntlr2_handoff_length; /* PHY attributes */ phys_addr_t phy_handoff_base; phys_addr_t phy_base; size_t phy_total_length; - size_t phy_handoff_length; + int phy_handoff_length; /* PHY engine attributes */ phys_addr_t phy_engine_handoff_base; size_t phy_engine_total_length; - size_t phy_engine_handoff_length; + int phy_engine_handoff_length; /* Calibration attributes */ phys_addr_t train_imem_base; |